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1. 发明授权

US08261214B2 Pattern layout creation method, program product, and semiconductor device manufacturing method 有权
标题翻译：图案布局创建方法，程序产品和半导体器件制造方法
公开(公告)号：US08261214B2
公开(公告)日：2012-09-04
申请号：US12630048
申请日：2009-12-03
申请人： Shimon Maeda , Masahiro Miyairi , Soichi Inoue
发明人： Shimon Maeda , Masahiro Miyairi , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A graph in which patterns are each regarded as nodes and nodes of patterns adjacent to each other at a first distance are connected with each other by an edge is produced, each of the patterns is classified into two types so that the two patterns corresponding to the nodes at both ends of the edge are types different to each other, a classification result is corrected by grouping the patterns in each node cluster connected by the edge or each node cluster connected via the node by the edge, and by inverting each of types of a pattern belonging to a same group as that of one pattern, out of a pair of patterns that are classified into a same type and that belong to respectively different groups adjacent to each other at a second distance, and a pattern layout diagram is created based on the corrected classification result.
摘要翻译：每个图形被认为是在第一距离处彼此相邻的图案的节点和节点之间的图形被生成，每个图案被分成两种类型，使得对应于边缘两端的节点是彼此不同的类型，分类结果通过将由边缘连接的每个节点簇中的模式或通过该节点连接的每个节点集合的边缘分组，并将每种类型的在一对图案中属于与一种图案相同的组合的图案，其分为相同类型并且分别属于彼此相邻的第二距离的不同组，并且基于图案布局图对正确的分类结果。

2. 发明申请

US20100191357A1 PATTERN LAYOUT CREATION METHOD, PROGRAM PRODUCT, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：图案布局创建方法，程序产品和半导体器件制造方法
公开(公告)号：US20100191357A1
公开(公告)日：2010-07-29
申请号：US12630048
申请日：2009-12-03
申请人： Shimon Maeda , Masahiro Miyairi , Soichi Inoue
发明人： Shimon Maeda , Masahiro Miyairi , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A graph in which patterns are each regarded as nodes and nodes of patterns adjacent to each other at a first distance are connected with each other by an edge is produced, each of the patterns is classified into two types so that the two patterns corresponding to the nodes at both ends of the edge are types different to each other, a classification result is corrected by grouping the patterns in each node cluster connected by the edge or each node cluster connected via the node by the edge, and by inverting each of types of a pattern belonging to a same group as that of one pattern, out of a pair of patterns that are classified into a same type and that belong to respectively different groups adjacent to each other at a second distance, and a pattern layout diagram is created based on the corrected classification result.
摘要翻译：每个图形被认为是在第一距离处彼此相邻的图案的节点和节点之间的图形被生成，每个图案被分成两种类型，使得对应于边缘两端的节点是彼此不同的类型，分类结果通过将由边缘连接的每个节点簇中的模式或通过该节点连接的每个节点集合的边缘分组，并将每种类型的在一对图案中属于与一种图案相同的组合的图案，其分为相同类型并且分别属于彼此相邻的第二距离的不同组，并且基于图案布局图对正确的分类结果。

3. 发明申请

US20100067777A1 EVALUATION PATTERN GENERATING METHOD, COMPUTER PROGRAM PRODUCT, AND PATTERN VERIFYING METHOD 审中-公开
标题翻译：评估模式生成方法，计算机程序产品和模式验证方法
公开(公告)号：US20100067777A1
公开(公告)日：2010-03-18
申请号：US12536900
申请日：2009-08-06
申请人： Katsuyoshi Kodera , Satoshi Tanaka , Shimon Maeda , Suigen Kyoh , Soichi Inoue , Ryuji Ogawa
发明人： Katsuyoshi Kodera , Satoshi Tanaka , Shimon Maeda , Suigen Kyoh , Soichi Inoue , Ryuji Ogawa
IPC分类号： G06K9/00
CPC分类号： G03F1/44 , G03F1/36
摘要： An evaluation pattern generating method including dividing a peripheral area of an evaluation target pattern into a plurality of meshes; calculating an image intensity of a circuit pattern when the evaluation target pattern is transferred onto a wafer by a lithography process in a case where a mask function value is given to a predetermined mesh; calculating a mask function value of the mesh so that a cost function of the image intensity, in which an optical image characteristic amount that affects a transfer performance of the evaluation target pattern to the wafer is set to the image intensity, satisfies a predetermined reference when evaluating a lithography performance of the evaluation target pattern; and generating an evaluation pattern corresponding to the mask function value.
摘要翻译： 1.一种评价图案生成方法，包括将评价对象图案的周边区域划分为多个网格; 当将掩模函数值赋予预定网格时，通过光刻处理将评估对象图案转印到晶片上时，计算电路图案的图像强度; 计算网格的掩码函数值，使得影响评估对象图案对晶片的转印性能的光学图像特征量被设置为图像强度的图像强度的成本函数满足预定参考，当评估目标模式的光刻性能评估; 以及生成与所述掩模功能值对应的评估图案。

4. 发明申请

US20090031262A1 MASK PATTERN FORMATION METHOD, MASK PATTERN FORMATION APPARATUS, AND LITHOGRAPHY MASK 审中-公开
标题翻译：掩模图案形成方法，掩模图案形成装置和平铺掩模
公开(公告)号：US20090031262A1
公开(公告)日：2009-01-29
申请号：US12179735
申请日：2008-07-25
申请人： Shimon Maeda , Suigen Kyoh , Soichi Inoue
发明人： Shimon Maeda , Suigen Kyoh , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A mask pattern formation method and apparatus capable of performing OPC and lithography verification and obtaining OPC result, and a lithography mask are provided. The method of forming a mask pattern from a design layout of a semiconductor integrated circuit comprises inputting a design layout, performing first OPC on the design layout, calculating a first evaluation value for a finished planar shape of a resist pattern corresponding to the design layout based on the first OPC, determining whether the first evaluation value satisfies a predetermined value, if the first evaluation value does not satisfy the predetermined value, locally altering the design layout, performing second OPC on the altered design layout, calculating a second evaluation value for the altered design layout, performing second determination, and if the second evaluation value satisfies the predetermined value, outputting the result of OPC and the first and second evaluation values.
摘要翻译：提供了能够执行OPC和光刻验证并获得OPC结果的掩模图案形成方法和装置，以及光刻掩模。从半导体集成电路的设计布局形成掩模图案的方法包括输入设计布局，在设计布局上执行第一OPC，计算与设计布局相对应的抗蚀剂图案的成品平面形状的第一评估值在第一OPC上，确定第一评估值是否满足预定值，如果第一评估值不满足预定值，则局部改变设计布局，在改变的设计布局上执行第二OPC，计算第二评估值改变设计布局，执行第二确定，以及如果第二评估值满足预定值，则输出OPC的结果以及第一和第二评估值。

5. 发明授权

US08654313B2 Exposing method and method of manufacturing semiconductor device 失效
标题翻译：揭示半导体器件制造方法和方法
公开(公告)号：US08654313B2
公开(公告)日：2014-02-18
申请号：US12952835
申请日：2010-11-23
申请人： Masanori Takahashi , Takashi Sato , Satoshi Tanaka , Soichi Inoue , Takamasa Takaki
发明人： Masanori Takahashi , Takashi Sato , Satoshi Tanaka , Soichi Inoue , Takamasa Takaki
IPC分类号： G03B27/32 , G03B27/54 , G03B27/72 , G03B27/52
CPC分类号： G03F7/2016 , G03F7/70408 , H01L21/0274
摘要： According to one embodiment, on a substrate, a resist layer is laminated on an upper side of a pattern formation layer on which a desired pattern is formed. A diffraction pattern that diffracts exposure light irradiated on the substrate is formed further on the upper side than the resist layer. Overall exposure is performed from above the diffraction pattern using a deformed light having illumination light source shape determined according to the desired pattern. Diffracted light diffracted on the diffraction pattern by the exposure is irradiated on the resist layer.
摘要翻译：根据一个实施例，在基板上，在其上形成有所需图案的图案形成层的上侧层压抗蚀剂层。衍射照射在基板上的曝光光的衍射图案进一步形成在抗蚀剂层的上侧。使用具有根据期望图案确定的照明光源形状的变形光从衍射图案上方进行总体曝光。通过曝光在衍射图案上衍射的衍射光被照射在抗蚀剂层上。

6. 发明授权

US08086973B2 Pattern management method and pattern management program 失效
标题翻译：模式管理方法和模式管理程序
公开(公告)号：US08086973B2
公开(公告)日：2011-12-27
申请号：US11958465
申请日：2007-12-18
申请人： Kenji Yoshida , Soichi Inoue
发明人： Kenji Yoshida , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A pattern management method includes extracting patterns having process margins equal to or below a predetermined value from a chip layout of an integrated circuit, screening a plurality of types of representative patterns from the extracted pattern, extracting patterns closest to the most outer periphery of the chip from the representative patterns, and representatively managing the extracted patterns which is closest to the most outer periphery of the chip.
摘要翻译：图案管理方法包括从集成电路的芯片布局提取具有等于或低于预定值的处理余量的图案，从提取的图案中筛选多种类型的代表图案，提取最靠近芯片的最外周边的图案并且代表性地管理最靠近芯片的最外围的提取图案。

7. 发明申请

US20110177458A1 EXPOSURE DETERMINING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：曝光测定方法，制造半导体器件的方法和计算机程序产品
公开(公告)号：US20110177458A1
公开(公告)日：2011-07-21
申请号：US13007238
申请日：2011-01-14
申请人： Toshiya KOTANI , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
发明人： Toshiya KOTANI , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
IPC分类号： G03F7/20 , G06F17/50
CPC分类号： G03F7/70425 , G03F7/70558
摘要： According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.
摘要翻译：根据一个实施例，获取形成在掩模上的掩模图案与期望的掩模图案之间的二维形状参数的偏差量分布作为掩模图案图。使得当在掩模经受曝光拍摄以形成基板上的图案和在基板上形成图案之后形成的基板上的图案之间的二维形状参数的偏移量适合在预定范围内时，确定曝光基于掩模图案图，在基板上形成图案的曝光中的每个位置。

8. 发明申请

US20110122390A1 EXPOSING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND EXPOSURE APPARATUS 失效
标题翻译：曝光方法，制造半导体器件的方法和曝光装置
公开(公告)号：US20110122390A1
公开(公告)日：2011-05-26
申请号：US12952835
申请日：2010-11-23
申请人： Masanori TAKAHASHI , Takashi Sato , Satoshi Tanaka , Soichi Inoue , Takamasa Takaki
发明人： Masanori TAKAHASHI , Takashi Sato , Satoshi Tanaka , Soichi Inoue , Takamasa Takaki
IPC分类号： G03B27/72 , G03F7/20
CPC分类号： G03F7/2016 , G03F7/70408 , H01L21/0274
摘要： According to one embodiment, on a substrate, a resist layer is laminated on an upper side of a pattern formation layer on which a desired pattern is formed. A diffraction pattern that diffracts exposure light irradiated on the substrate is formed further on the upper side than the resist layer. Overall exposure is performed from above the diffraction pattern using a deformed light having illumination light source shape determined according to the desired pattern. Diffracted light diffracted on the resist layer.
摘要翻译：根据一个实施例，在基板上，在其上形成有所需图案的图案形成层的上侧层压抗蚀剂层。衍射照射在基板上的曝光光的衍射图案进一步形成在抗蚀剂层的上侧。使用具有根据期望图案确定的照明光源形状的变形光从衍射图案上方进行总体曝光。衍射光在抗蚀剂层上衍射。

9. 发明授权

US07821628B2 Mask defect inspection computer program product 有权
标题翻译：面膜缺陷检查计算机程序产品
公开(公告)号：US07821628B2
公开(公告)日：2010-10-26
申请号：US11980640
申请日：2007-10-31
申请人： Shinji Yamaguchi , Soichi Inoue , Satoshi Tanaka , Mari Inoue
发明人： Shinji Yamaguchi , Soichi Inoue , Satoshi Tanaka , Mari Inoue
IPC分类号： G01N21/00
CPC分类号： G03F1/84
摘要： A mask defect inspecting method comprises preparing detection sensitivities of defects on a plurality of portions of a mask pattern on a photomask, the detection sensitivities being determined according to influences of the defects upon a wafer, and inspecting defects on the plurality of portions based on the detection sensitivities.
摘要翻译：掩模缺陷检查方法包括：对光掩模上的掩模图案的多个部分上的缺陷的检测灵敏度进行准备，检测灵敏度根据晶片上的缺陷的影响确定，并且基于所述多个部分检查多个部分的缺陷检测灵敏度。

10. 发明授权

US07541136B2 Mask, manufacturing method for mask, and manufacturing method for semiconductor device 失效
标题翻译：掩模，掩模的制造方法和半导体器件的制造方法
公开(公告)号：US07541136B2
公开(公告)日：2009-06-02
申请号：US11472452
申请日：2006-06-22
申请人： Kyoko Izuha , Hideki Kanai , Soichi Inoue , Shingo Kanamitsu , Shinichi Ito
发明人： Kyoko Izuha , Hideki Kanai , Soichi Inoue , Shingo Kanamitsu , Shinichi Ito
IPC分类号： G03C5/00
CPC分类号： G03F1/30 , G03F1/32 , G03F7/70641 , G03F7/70683
摘要： Disclosed is a mask comprising a first area including a first surrounding area in which a halftone phase shift film or a stacked film of a halftone phase shift film and an opaque film is provided on a transparent substrate, and a first opening area surrounded by the first surrounding area, and a second area including a second surrounding area in which a halftone phase shift film is provided on the transparent substrate and a second opening area surrounded by the second surrounding area, wherein a transparent film is provided in at least a part of the second opening area, the transparent film being configured to give a predetermined phase difference to exposure light passing through that part of the second opening area in which the transparent film is provided relative to exposure light passing through the second surrounding area.
摘要翻译：公开了一种掩模，其包括：第一区域，包括第一周围区域，在透明基板上设置有半色调相移膜或半色调相移膜的叠层膜和不透明膜;以及第一开口区域，以及第二区域，其包括在透明基板上设置半色调相移膜的第二周围区域和由第二周围区域围绕的第二开口区域，其中在至少一部分中设置透明膜第二开口区域，所述透明膜被配置为相对于穿过所述第二周围区域的曝光光而通过其中设置有所述透明膜的所述第二开口区域的那部分的曝光而给予预定的相位差。

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