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    • 3. 发明授权
    • Memory device structure with decoders in a device level separate from the array level
    • 存储器件结构,其中解码器的器件级别与阵列级别分开
    • US09111597B2
    • 2015-08-18
    • US13721523
    • 2012-12-20
    • Shih-Hung Chen
    • Shih-Hung Chen
    • H01L23/48G11C8/10G11C5/02
    • G11C8/10G11C5/025
    • A memory device structure and method of fabricating the memory device structure is described. The memory device structure has a memory array disposed in a array level and peripheral circuitry, including decoders and other peripheral circuitry, disposed in a device level. The array of memory cells has a perimeter that defines a cylinder that extends above and beneath the array of memory cells. The decoders and the other peripheral circuitry or at least part of the decoders and the other peripheral circuitry are disposed within the cylinder in the device level. The memory device structure also includes a plurality of pads in a pad level. A first plurality of inter-level conductive lines electrically couples the decoders to the bit lines and word lines in the array of memory cells.
    • 描述了一种用于制造存储器件结构的存储器件结构和方法。 存储器件结构具有设置在阵列级的存储器阵列和设置在器件级的外围电路,包括解码器和其它外围电路。 存储器单元阵列具有限定在存储器单元阵列上方和下方延伸的圆柱体的周边。 解码器和其它外围电路或解码器和其它外围电路的至少一部分设置在装置级内的气缸内。 存储器件结构还包括垫级别中的多个焊盘。 第一多个级间导电线将解码器电耦合到存储器单元阵列中的位线和字线。
    • 4. 发明授权
    • NAND flash with non-trapping switch transistors
    • NAND闪存与非陷阱开关晶体管
    • US09082656B2
    • 2015-07-14
    • US13294852
    • 2011-11-11
    • Shih-Hung ChenHang-Ting LueYen-Hao Shih
    • Shih-Hung ChenHang-Ting LueYen-Hao Shih
    • H01L27/115
    • H01L27/1157H01L27/11578
    • A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.
    • 一种用于存储器阵列的制造方法包括首先在多个半导体条上形成多层电介质材料,然后在开关晶体管区域中暴露多层叠层。 在开关晶体管区域中暴露的多层堆叠被处理以形成不同于介电电荷俘获结构的栅介质结构。 然后形成字线和选择线。 介质电荷俘获存储器单元的3D阵列包括存储器单元的NAND串的堆叠。 多个开关晶体管耦合到NAND串,开关晶体管包括栅极电介质结构,其中栅极电介质结构不同于介电电荷俘获结构。