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1. 发明申请

US20130245978A1 SYSTEMS AND METHODS OF CONTROLLING SEMICONDUCTOR WAFER FABRICATION PROCESSES 有权
标题翻译：控制半导体波形制造工艺的系统和方法
公开(公告)号：US20130245978A1
公开(公告)日：2013-09-19
申请号：US13419952
申请日：2012-03-14
申请人： Shih-Hung CHEN , Ying Xiao , Chin-Hsiang Lin
发明人： Shih-Hung CHEN , Ying Xiao , Chin-Hsiang Lin
IPC分类号： G06F15/00 , G01B11/26
CPC分类号： H01L21/67259 , H01L21/681 , H01L21/68764
摘要： A system and method of controlling a semiconductor wafer fabrication process. The method includes positioning a semiconductor wafer on a wafer support assembly in a wafer processing module. A signal is transmitted from a signal emitter positioned at a predetermined transmission angle relative to an axis normal to the wafer support assembly to check leveling of the wafer in the module, so that the signal is reflected from the wafer. The embodiment includes monitoring for the reflected signal at a predetermined reflectance angle relative to the axis normal to the wafer support assembly at a signal receiver. A warning indication is generated if the reflected signal is not received at the signal receiver.
摘要翻译：一种控制半导体晶片制造工艺的系统和方法。该方法包括将半导体晶片定位在晶片处理模块中的晶片支撑组件上。信号从相对于垂直于晶片支撑组件的轴线以预定的传输角定位的信号发射器传输，以检查模块中晶片的调平，使得信号从晶片反射。该实施例包括在信号接收器处相对于垂直于晶片支撑组件的轴以预定的反射角监视反射信号。如果在信号接收器处未接收到反射信号，则会产生警告指示。

2. 发明申请

US20130322990A1 LOADPORT BRIDGE FOR SEMICONDUCTOR FABRICATION TOOLS 有权
标题翻译：半导体制造工具的负载桥
公开(公告)号：US20130322990A1
公开(公告)日：2013-12-05
申请号：US13486024
申请日：2012-06-01
申请人： Shih-Hung CHEN , Ying XIAO , Chin-Hsiang LIN
发明人： Shih-Hung CHEN , Ying XIAO , Chin-Hsiang LIN
IPC分类号： H01L21/677
CPC分类号： H01L21/6773 , H01L21/67733 , H01L21/67775
摘要： A wafer handling system with apparatus for transporting wafers between semiconductor fabrication tools. In one embodiment, the apparatus is a loadport bridge mechanism including an enclosure having first and second mounting ends, a docking port at each end configured and dimensioned to interface with a loadport of a semiconductor tool, and at least one wafer transport robot operable to transport a wafer between the docking ports. The wafer transport robot hands off or receives a wafer to/from a tool robot at the loadports of a first and second tool. The bridge mechanism allows one or more wafers to be transferred between loadports of different tools on an individual basis without reliance on the FAB's automated material handling system (AMHS) for bulk wafer transport inside a wafer carrier such as a FOUP or others.
摘要翻译：一种具有用于在半导体制造工具之间传输晶片的装置的晶片处理系统。在一个实施例中，该装置是装载端口机构，其包括具有第一和第二安装端的外壳，每个端部处的对接端口被构造和尺寸设计成与半导体工具的承载端口相接合，以及至少一个可运输的晶片传送机械手在对接端口之间的晶片。晶片传送机器人在第一和第二工具的载荷端口移动或接收来自工具机器人的晶片。桥接机构允许一个或多个晶片在不同工具的载荷端口之间单独传输，而不依赖于FAB的自动化材料处理系统（AMHS），用于在诸如FOUP或其它晶片载体之间的体晶片传输。

3. 发明申请

US20140193973A1 METHOD FOR FORMING INTERLAYER CONNECTORS TO A STACK OF CONDUCTIVE LAYERS 有权
标题翻译：将层间连接器形成到导电层堆叠的方法
公开(公告)号：US20140193973A1
公开(公告)日：2014-07-10
申请号：US13735922
申请日：2013-01-07
申请人： Shih-Hung CHEN
发明人： Shih-Hung CHEN
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , H01L21/0273 , H01L21/32139 , H01L21/76838 , H01L27/11548 , H01L27/11575
摘要： A method forms interlayer connectors extending to conductive layers of a stack of W conductive layers interleaved with dielectric layers. The stack is etched to expose landing areas at W−1 conductive layers using a set of M etch masks. For each etch mask m, m going from 0 to M−1, there is a first etching step, at least one mask trimming step, and a subsequent etching step following each trimming step. The etch mask may cover Nm+1 of the landing areas and the open etch region may cover Nm of the landing areas. N equals 2 plus the number of trimming steps. The trimming step may be carried out so that the increased size open etch region overlies an additional 1/N of the landing areas. Part of the stack surface may be shielded during the removing step to create dummy areas without contact openings.
摘要翻译：一种方法形成延伸到与电介质层交错的W导电层的堆叠的导体层的层间连接。使用一组M蚀刻掩模蚀刻堆叠以暴露W-1导电层的着陆区域。对于从0到M-1的每个蚀刻掩模m，m，在每个修整步骤之后，存在第一蚀刻步骤，至少一个掩模修剪步骤和随后的蚀刻步骤。蚀刻掩模可以覆盖着陆区域的Nm + 1，并且开放蚀刻区域可以覆盖着陆区域的Nm。 N等于2加上修剪步骤的数量。可以进行修整步骤，使得增大的开口蚀刻区域覆盖附加的1 / N的着陆区域。在去除步骤期间可以屏蔽堆叠表面的一部分以产生没有接触开口的虚拟区域。

4. 发明申请

US20120184097A1 Reduced Number of Masks for IC Device with Stacked Contact Levels 有权
标题翻译：具有堆叠接触电平的IC器件减少数量的掩模
公开(公告)号：US20120184097A1
公开(公告)日：2012-07-19
申请号：US13049303
申请日：2011-03-16
申请人： Shih-Hung CHEN , Hang-Ting LUE
发明人： Shih-Hung CHEN , Hang-Ting LUE
IPC分类号： H01L23/538 , H01L21/308 , C23F1/08
CPC分类号： H01L21/67069 , H01L21/76805 , H01L21/76816 , H01L21/76838 , H01L23/5226 , H01L27/0207 , H01L27/0688 , H01L27/11286 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2N levels of interconnect contact regions at the stack of contact levels. According to some examples, 2x−1 contact levels are etched for each mask sequence number x, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. Methods create the interconnect contact regions aligned with landing areas at the contact levels.
摘要翻译：三维堆叠IC器件在互连区域具有一层接触电平。根据本发明的一些示例，其仅需要一组N个蚀刻掩模以在接触电平的堆叠处产生多达且包括2N级的互连接触区域。根据一些示例，对于每个掩码序列号x蚀刻2x-1接触电平，x是掩模的序列号，使得对于一个掩模x = 1，对于另一个掩模x = 2，依此类推，x = N 。方法创建互连接触区域与接触层面上的着陆区域对齐。

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