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1. 发明申请

US20120184097A1 Reduced Number of Masks for IC Device with Stacked Contact Levels 有权
标题翻译：具有堆叠接触电平的IC器件减少数量的掩模
公开(公告)号：US20120184097A1
公开(公告)日：2012-07-19
申请号：US13049303
申请日：2011-03-16
申请人： Shih-Hung CHEN , Hang-Ting LUE
发明人： Shih-Hung CHEN , Hang-Ting LUE
IPC分类号： H01L23/538 , H01L21/308 , C23F1/08
CPC分类号： H01L21/67069 , H01L21/76805 , H01L21/76816 , H01L21/76838 , H01L23/5226 , H01L27/0207 , H01L27/0688 , H01L27/11286 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2N levels of interconnect contact regions at the stack of contact levels. According to some examples, 2x−1 contact levels are etched for each mask sequence number x, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. Methods create the interconnect contact regions aligned with landing areas at the contact levels.
摘要翻译：三维堆叠IC器件在互连区域具有一层接触电平。根据本发明的一些示例，其仅需要一组N个蚀刻掩模以在接触电平的堆叠处产生多达且包括2N级的互连接触区域。根据一些示例，对于每个掩码序列号x蚀刻2x-1接触电平，x是掩模的序列号，使得对于一个掩模x = 1，对于另一个掩模x = 2，依此类推，x = N 。方法创建互连接触区域与接触层面上的着陆区域对齐。

2. 发明申请

US20110140193A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110140193A1
公开(公告)日：2011-06-16
申请号：US13032836
申请日：2011-02-23
申请人： Sheng-Chih LAI , Hang-Ting LUE
发明人： Sheng-Chih LAI , Hang-Ting LUE
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/517 , H01L29/513 , H01L29/66833 , H01L29/792
摘要： A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.
摘要翻译：提供了具有非易失性存储器的半导体器件及其制造方法。半导体器件包括基底材料和堆叠结构。设置在基材上的堆叠结构至少包括隧穿层，捕获层和电介质层。捕获层设置在隧道层上。电介质层具有介电常数并且设置在捕获层上。当电介质层进行处理时，电介质层从第一固态转变为第二固态。

3. 发明申请

US20100193859A1 BLOCKING DIELECTRIC ENGINEERED CHARGE TRAPPING MEMORY CELL WITH HIGH SPEED ERASE 有权
标题翻译：阻塞电路工程电荷捕捉存储单元高速擦除
公开(公告)号：US20100193859A1
公开(公告)日：2010-08-05
申请号：US12763006
申请日：2010-04-19
申请人： Sheng Chih LAI , Hang-Ting LUE , Chien Wei LIAO
发明人： Sheng Chih LAI , Hang-Ting LUE , Chien Wei LIAO
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/115 , G11C16/0466 , G11C16/0483 , H01L21/28282 , H01L27/11568 , H01L29/513 , H01L29/792
摘要： A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.
摘要翻译：带隙设计的电荷捕获存储单元包括电荷捕获元件，其通过具有介电常数的金属掺杂氧化硅材料的阻挡层（例如掺铝氧化硅）与栅极分离，并与半导体本体分离，包括通道由工程隧道电介质。

4. 发明申请

US20120236642A1 INTEGRATED CIRCUIT SELF ALIGNED 3D MEMORY ARRAY AND MANUFACTURING METHOD 有权
标题翻译：集成电路自对准3D存储阵列和制造方法
公开(公告)号：US20120236642A1
公开(公告)日：2012-09-20
申请号：US13482843
申请日：2012-05-29
申请人： Hang-Ting LUE
发明人： Hang-Ting LUE
IPC分类号： G11C11/34 , G11C16/04 , H01L21/283
CPC分类号： G11C5/06 , G11C5/02 , H01L27/0688 , H01L27/101 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.
摘要翻译： 3D存储器件包括多个由绝缘材料隔开的导电材料条带形式的脊形叠层，排列成可通过解码电路耦合到读出放大器的位线。导电材料条具有在脊形叠层的侧面上的侧表面。布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。导线符合堆叠的表面。存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。存储器元件是可编程的，如抗熔丝或电荷捕获结构。 3D存储器仅使用两层用于多层的关键掩模。

5. 发明申请

US20090045452A1 Structure and Method of Sub-Gate NAND Memory with Bandgap Engineered SONOS Devices 有权
标题翻译：具有带隙工程SONOS器件的子栅极NAND存储器的结构和方法
公开(公告)号：US20090045452A1
公开(公告)日：2009-02-19
申请号：US12175297
申请日：2008-07-17
申请人： Hang-Ting LUE , Hao Ming Lien
发明人： Hang-Ting LUE , Hao Ming Lien
IPC分类号： H01L47/00
CPC分类号： G11C16/0466 , G11C16/0491 , H01L21/28273 , H01L27/115 , H01L27/11568 , H01L29/792
摘要： A bandgap engineered SONOS device structure for design with various AND architectures. The BE-SONOS device structure comprises a spacer oxide disposed between a control gate overlaying an oxide-nitride-oxide-nitride-oxide stack and a sub-gate overlaying a gate oxide. In one example, a BE-SONOS sub-gate-AND array architecture has multiple strings of SONONOS devices with sub-gate lines and diffusion bit lines. In another example, a BE-SONOS sub-gate-AND architecture has multiple strings of SONONOS devices with sub-gate lines, relying on the sub-gate lines that create inversions to substitute for the diffusion bit lines.
摘要翻译：带隙设计的SONOS设备结构，具有各种AND架构设计。 BE-SONOS器件结构包括设置在覆盖氧化物 - 氮化物 - 氧化物 - 氮化物 - 氧化物堆叠的控制栅极和覆盖栅极氧化物的子栅极之间的隔离氧化物。在一个示例中，BE-SONOS子栅极与阵列架构具有多个具有子栅极线和扩散位线的SONONOS器件串。在另一个示例中，BE-SONOS子门-OR架构具有多个具有子栅极线的SONONOS器件串，依赖于产生反转来代替扩散位线的子栅极线。

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