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1. 发明申请

US20140306344A1 WIRING STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING WIRING STRUCTURE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：布线结构，包括布线结构的半导体器件，以及制造半导体器件的方法
公开(公告)号：US20140306344A1
公开(公告)日：2014-10-16
申请号：US14313026
申请日：2014-06-24
申请人： Shigetoshi Sugawa , Akinobu Teramoto , Rihito Kuroda , Gu Xun
发明人： Shigetoshi Sugawa , Akinobu Teramoto , Rihito Kuroda , Gu Xun
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/02063 , H01L21/0212 , H01L21/02126 , H01L21/02167 , H01L21/02211 , H01L21/02274 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76802 , H01L21/76807 , H01L21/76808 , H01L21/76831 , H01L21/76843 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： There is provided with a wiring structure. The wiring stracture has a damascene wiring structure including a metal wiring. The metal wiring is provided in direct contact with an upper surface of a barrier film (SiC(O, N) film) containing silicon (Si), carbon (C), and at least one of oxygen (O) and nitrogen (N) as constituent components.
摘要翻译：设有布线结构。布线结构具有包括金属布线的镶嵌布线结构。金属布线与含有硅（Si），碳（C）和氧（O）和氮（N）中的至少一种的阻挡膜（SiC（O，N）膜）的上表面直接接触，作为组成部分。

2. 发明授权

US09214489B2 Photodiode and method for producing the same, photodiode array, spectrophotometer and solid-state imaging device 有权
标题翻译：光电二极管及其制造方法，光电二极管阵列，分光光度计和固态成像装置
公开(公告)号：US09214489B2
公开(公告)日：2015-12-15
申请号：US14124129
申请日：2012-06-04
申请人： Shigetoshi Sugawa , Rihito Kuroda
发明人： Shigetoshi Sugawa , Rihito Kuroda
IPC分类号： H01L31/062 , H01L27/146 , H01L31/06 , H01L31/18 , G01J3/28
CPC分类号： G01J3/2803 , G01J3/2823 , G01J2003/2813 , H01L27/1446 , H01L27/14601 , H01L27/14609 , H01L27/14643 , H01L31/02363 , H01L31/06 , H01L31/103 , H01L31/18 , H01L31/1804 , H01L31/1864 , Y02E10/50 , Y02E10/547 , Y02P70/521
摘要： Provided is a photodiode having a high-concentration layer on its surface, in which the high-concentration layer is formed so that the thickness of a non-depleted region is larger than the roughness of an interface between silicon and an insulator layer, and is smaller than a penetration depth of ultraviolet light.
摘要翻译：提供了在其表面上具有高浓度层的光电二极管，其中形成高浓度层，使得非耗尽区的厚度大于硅与绝缘体层之间的界面的粗糙度，并且是小于紫外线的穿透深度。

3. 发明授权

US08183670B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08183670B2
公开(公告)日：2012-05-22
申请号：US11651034
申请日：2007-01-09
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto , Hiroshi Akahori , Keiichi Nii
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto , Hiroshi Akahori , Keiichi Nii
IPC分类号： H01L29/04
CPC分类号： H01L21/3185 , H01L21/30604 , H01L21/31654 , H01L21/318 , H01L29/6659
摘要： In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
摘要翻译：在形成在具有大致（110）晶面取向的硅表面上的半导体器件中，硅表面变平，使得表面Ra的算术平均偏差不大于0.15nm，优选为0.09nm，这使得能够制造高迁移率的n-MOS晶体管。通过在脱氧H 2 O或低OH密度气氛中清洗硅表面，通过在氧自由基气氛中重复自牺牲氧化物膜的沉积工艺和自牺牲氧化物膜的去除工艺来获得这种扁平化的硅表面，或通过氢或重氢强烈地终止硅表面。自牺牲氧化膜的沉积工艺可以通过各向同性氧化进行。

4. 发明授权

US08093918B2 Electronic device identifying method and electronic device comprising identification means 失效
标题翻译：电子设备识别方法和包括识别装置的电子设备
公开(公告)号：US08093918B2
公开(公告)日：2012-01-10
申请号：US12859100
申请日：2010-08-18
申请人： Toshiyuki Okayasu , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Toshiyuki Okayasu , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： G01R31/36
CPC分类号： H01L23/544 , G01R31/31718 , G11C2029/4402 , H01L21/76254 , H01L22/14 , H01L2223/5444 , H01L2924/0002 , Y10T29/49004 , H01L2924/00
摘要： An electronic device that includes an actual operation circuit that operates during an actual operation of the electronic device, a second test circuit and a third test circuit that operate during a test of the electronic device, and a power supply section. The power supply section, during the actual operation of the electronic device, does not apply a power supply voltage to the second test circuit and applies power supply voltages to the actual operation circuit and the third test circuit. The power supply section, to obtain identification of the electronic device, applies a power supply voltage to the second test circuit.
摘要翻译：一种电子设备，包括在电子设备的实际操作期间操作的实际操作电路，在电子设备的测试期间操作的第二测试电路和第三测试电路以及电源部分。在电子设备的实际操作期间，电源部分不向第二测试电路施加电源电压，并且向实际操作电路和第三测试电路施加电源电压。为了获得电子设备的识别，电源部分向第二测试电路施加电源电压。

5. 发明授权

US07848828B2 Method and apparatus for managing manufacturing equipment, method for manufacturing device thereby 失效
标题翻译：用于管理制造设备的方法和装置，由此制造装置的方法
公开(公告)号：US07848828B2
公开(公告)日：2010-12-07
申请号：US12055310
申请日：2008-03-25
申请人： Toshiyuki Okayasu , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Toshiyuki Okayasu , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： G05B11/01 , G06F19/00 , G01B5/28 , H01L23/58
CPC分类号： G05B19/4184 , G05B2219/31483 , G05B2219/45031 , H01L22/20 , H01L22/34 , H01L2924/0002 , Y02P90/14 , Y02P90/22 , H01L2924/00
摘要： Provided is a method for managing manufacturing apparatuses used in a managed production line including a plurality of manufacturing processes for manufacturing an electronic device, each of the apparatuses being used in one or more of the processes. The method includes acquiring a property of a reference device manufactured in a predetermined reference production line including the manufacturing processes to be performed, performing at least one of the manufacturing processes in the managed production line, performing the other manufacturing processes in the reference production line, and manufacturing a comparison device. The method further includes measuring a property of the comparison device, comparing the measured properties of the reference and the comparison devices, and judging whether a manufacturing apparatus used in the at least one manufacturing process in the managed production line is defective or not, based on a property difference between the reference and the comparison devices.
摘要翻译：提供一种用于管理包括用于制造电子设备的多个制造过程的管理生产线中的制造设备的方法，每个设备在一个或多个处理中使用。该方法包括获取在预定参考生产线中制造的参考装置的特性，包括要执行的制造过程，执行管理生产线中的至少一个制造过程，在参考生产线中执行其他制造过程，并制造比较装置。该方法还包括测量比较装置的性质，比较参考和比较装置的测量属性，以及基于管理生产线中的至少一个制造过程中使用的制造装置是否有缺陷，基于参考和比较设备之间的属性差异。

6. 发明申请

US20070105523A1 Low noise amplifier 审中-公开
标题翻译：低噪声放大器
公开(公告)号：US20070105523A1
公开(公告)日：2007-05-10
申请号：US10560703
申请日：2004-06-11
申请人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： H04B1/10 , H04B1/28 , H04B1/16
CPC分类号： H01L21/82385 , H01L21/823807 , H01L27/092 , H01L29/785 , H03F1/26 , H03F2200/372 , H03G1/0029 , H03G1/007
摘要： A low noise amplifier is assumed to comprise an MIS transistor and to amplify an input signal keeping noise at a low level, and the MIS transistor comprises a semiconductor substrate for comprising a first crystal plane as a principal plane, a semiconductor structure, formed as a part of the semiconductor substrate, for comprising a pair of sidewall planes defined by the second crystal plane different from the first crystal plane and a top plane defined by the third crystal plane different from the second crystal plane, a gate insulator of uniform thickness covering the principal plane, the sidewall planes and the top plane, a gate electrode for continuously covering the principal plane, the sidewall planes and the top plane on top of the gate insulator, and a single conductivity type diffusion area formed in the region to either side of the gate electrode in the semiconductor substrate and the semiconductor structure and continuously extending along the principal plane, the sidewall planes and the top plane. Such a configuration allows significant reduction of the 1/f noise and the signal distortion applied to an output signal by the low noise amplifier and therefore a circuit for compensating for the reduction of the amplitude is no longer of necessity, allowing reduction in size.
摘要翻译：假设低噪声放大器包括MIS晶体管并且将保持噪声保持在低电平的输入信号放大，并且MIS晶体管包括用于包括第一晶面作为主平面的半导体衬底，形成为所述半导体衬底的一部分包括由不同于所述第一晶体面的所述第二晶体面限定的一对侧壁平面和由与所述第二晶体面不同的所述第三晶体面限定的顶面，覆盖所述半导体衬底的均匀厚度的栅极绝缘体主平面，侧壁平面和顶面，用于连续覆盖主平面，侧壁平面和栅极绝缘体顶部的顶面的栅极，以及在该区域中形成的单一导电型扩散区域半导体衬底中的栅电极和半导体结构，并且沿着主平面连续延伸，侧壁p 车道和顶层飞机。这样的配置允许显着降低由低噪声放大器施加到输出信号的1 / f噪声和信号失真，因此不再需要用于补偿幅度减小的电路，从而允许尺寸减小。

7. 发明申请

US20060180840A1 Switched capacitor circuit and semiconductor integrated circuit thereof 审中-公开
标题翻译：开关电容电路及其半导体集成电路
公开(公告)号：US20060180840A1
公开(公告)日：2006-08-17
申请号：US10560397
申请日：2004-06-11
申请人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/66787 , H01L21/823807 , H01L21/82385 , H01L27/092
摘要： A rectangular parallelepiped projecting portion (21) having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the projecting portion (21), thereby generating a MOS transistor. By connecting in parallel a p-channel MOS transistor and an n-channel MOS transistor produced as described above, a switch of a switched capacitor circuit is configured, thereby reducing a leak current and a DC offset of the switched capacitor circuit.
摘要翻译：在硅衬底上形成具有H B高度和W B B的宽度的长方体的突出部分（21），并且栅极氧化膜形成在突出部分（21）的顶表面和侧表面的一部分，从而产生MOS晶体管。通过并联连接如上所述制造的p沟道MOS晶体管和n沟道MOS晶体管，构造开关电容器电路的开关，从而减小开关电容器电路的漏电流和DC偏移。

8. 发明申请

US20110110052A1 MULTILAYER WIRING BOARD 有权
标题翻译：多层接线板
公开(公告)号：US20110110052A1
公开(公告)日：2011-05-12
申请号：US12995514
申请日：2009-05-22
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Hiroshi Imai , Akinobu Teramoto
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Hiroshi Imai , Akinobu Teramoto
IPC分类号： H05K1/18 , H05K1/00
CPC分类号： H05K1/0218 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2223/6688 , H01L2924/0002 , H01L2924/19032 , H01L2924/3011 , H05K1/025 , H05K1/0265 , H05K3/4652 , H05K2201/0191 , H05K2201/0352 , H05K2201/0715 , H05K2201/096 , H05K2201/09618 , H05K2201/09727 , H05K2201/09972 , H01L2924/00
摘要： A multilayer wiring board 100 comprises a first wiring region 101 where wirings 103a and insulating layers 104a and 104b are alternately laminated, and a second wiring region 102 where a thickness H2 of an insulating layer 104 is twice or more a thickness H1 of the insulating layer in the first wiring region 101 and a width W2 of a wiring 103b is twice or more a width W1 of the wiring in the first wiring region 101. The first wiring region 101 and the second wiring region 102 are integrally formed on the same board.
摘要翻译：多层布线基板100包括：布线103a和绝缘层104a，104b交替层叠的第一布线区域101和绝缘层104的厚度H2为绝缘层的厚度H1的两倍以上的第二布线区域102 在第一布线区域101中，布线103b的宽度W2是第一布线区域101中的布线的宽度W1的两倍或更多倍。第一布线区域101和第二布线区域102一体地形成在同一个板上。

9. 发明授权

US07812595B2 Electronic device identifying method 失效
标题翻译：电子设备识别方法
公开(公告)号：US07812595B2
公开(公告)日：2010-10-12
申请号：US12032998
申请日：2008-02-18
申请人： Toshiyuki Okayasu , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Toshiyuki Okayasu , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： G01R31/28
CPC分类号： H01L23/544 , G01R31/31718 , G11C2029/4402 , H01L21/76254 , H01L22/14 , H01L2223/5444 , H01L2924/0002 , Y10T29/49004 , H01L2924/00
摘要： There is provided a device identifying method for identifying an electronic device including therein an actual operation circuit and a test circuit having a plurality of test elements provided therein, where the actual operation circuit operates during an actual operation of the electronic device and the test circuit operates during a test of the electronic device. The device identifying method includes measuring electrical characteristics of a plurality of test elements, storing identification information of an electronic device by storing the measured electrical characteristics of the respective test elements, obtaining identification information of a certain electronic device by measuring electrical characteristics of a plurality of test elements provided in the certain electronic device in order to identify the certain electronic device, comparing the identification information obtained in the identification information obtaining with the identification information stored in the identification information storing, and, when the obtained identification information matches the stored identification information, judging that the certain electronic device is the same as the electronic device associated with the stored identification information.
摘要翻译：提供一种用于识别其中包括实际操作电路的电子设备的装置识别方法和其中设置有多个测试元件的测试电路，其中实际操作电路在电子设备的实际操作期间操作并且测试电路操作在电子设备的测试期间。设备识别方法包括测量多个测试元件的电特性，通过存储所测量的各个测试元件的电特性来存储电子设备的识别信息，通过测量多个测试元件的电特性来获得某个电子设备的识别信息在特定电子设备中提供的测试元件，以识别某个电子设备，将获得的识别信息与存储在识别信息中的识别信息进行比较，并且当获得的识别信息与存储的识别信息相匹配时判断该电子装置与存储的识别信息相关联的电子装置相同。

10. 发明授权

US07774081B2 Manufacturing system, manufacturing method, managing apparatus, managing method and computer readable medium 失效
标题翻译：制造系统，制造方法，管理装置，管理方法和计算机可读介质
公开(公告)号：US07774081B2
公开(公告)日：2010-08-10
申请号：US12046457
申请日：2008-03-12
申请人： Toshiyuki Okayasu , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Toshiyuki Okayasu , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： G06F19/00 , G01N37/00 , G11C16/04 , H01R31/26 , H01L21/66
CPC分类号： G05B19/41875 , G05B2219/32221 , G05B2219/45031 , H01L22/20 , H01L22/34 , H01L2924/0002 , Y02P90/22 , H01L2924/00
摘要： There is provided a manufacturing system for manufacturing an electronic device through a plurality of manufacturing stages. The manufacturing system includes a plurality of manufacturing apparatuses performing processes corresponding to the plurality of manufacturing stages. The manufacturing system includes a manufacturing line that manufactures the electronic device, a manufacturing control section that causes the manufacturing line to manufacture a wafer having therein a test circuit including a plurality of transistors under measurement, a measuring section that measures an electrical characteristic of each of the plurality of transistors under measurement in the test circuit, an identifying section that identifies, among the plurality of manufacturing stages, a manufacturing stage in which a defect is generated, with reference to a distribution, on the wafer, of one or more transistors under measurement whose electrical characteristics do not meet a predetermined standard, and a setting changing section that changes a setting for a manufacturing apparatus that performs a process corresponding to the manufacturing stage in which the defect is generated.
摘要翻译：提供了一种用于通过多个制造阶段制造电子装置的制造系统。制造系统包括执行与多个制造阶段相对应的处理的多个制造装置。制造系统包括制造电子装置的制造线，使制造线制造其中具有测量电路的测试电路的晶片的制造控制部，测量各测量电路的电特性的测量部在测试电路中测量的多个晶体管，识别部分，其在多个制造阶段中，根据晶片上的一个或多个晶体管的分布，识别其中产生缺陷的制造阶段电气特性不符合预定标准的测量值，以及改变执行与生成缺陷的制造阶段相对应的处理的制造装置的设定的设定变更部。

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