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1. 发明申请

US20050002277A1 Electric timepiece 有权
标题翻译：电表
公开(公告)号：US20050002277A1
公开(公告)日：2005-01-06
申请号：US10493898
申请日：2003-03-04
申请人： Masami Fukuda , Kiyotaka Igarashi , Shinichi Komine , Ryoji Iwakura , Shigeru Morokawa
发明人： Masami Fukuda , Kiyotaka Igarashi , Shinichi Komine , Ryoji Iwakura , Shigeru Morokawa
IPC分类号： G01D5/241 , G04C3/14 , G04C17/00 , G04B19/04 , G04B19/06
CPC分类号： G01D5/2412 , G04C3/14 , G04C17/0066
摘要： An electric watch is characterized by including a transmitting circuit 6 for generating a plurality of transmitted signals, transmitting electrodes 1 and 2 for outputting the output signals generated by the transmitting circuit 6, a signal modulating member 3 composed of a rotor arranged adjacently to the transmitting electrodes 1 and 2 in a non-contact manner for modulating the transmitted signals, a receiving electrode 4 arranged adjacently to the signal modulating member 3 in a non-contact manner for receiving the transmitted signals modulated by the signal modulating member 3, a receiving circuit 7 for amplifying received signals received by the receiving electrode 4, and a detecting circuit 8 for detecting mechanical position information of the signal modulating member 3 based on the received signal amplified by the receiving circuit 7.
摘要翻译：电手表的特征在于包括用于产生多个发送信号的发送电路6，用于输出由发送电路6产生的输出信号的发送电极1和2，由与发送电路6相邻布置的转子组成的信号调制部件3 用于调制发射信号的非接触方式的电极1和2;以非接触方式布置在与信号调制构件3相邻的接收电极4，用于接收由信号调制构件3调制的发射信号;接收电路用于放大由接收电极4接收的接收信号的检测电路7以及用于基于由接收电路7放大的接收信号来检测信号调制部件3的机械位置信息的检测电路8。

2. 发明授权

US5815233A Optical device containing a liquid crystal element for changing optical characteristics of a lens element 失效
标题翻译：含有用于改变透镜元件的光学特性的液晶元件的光学装置
公开(公告)号：US5815233A
公开(公告)日：1998-09-29
申请号：US949815
申请日：1997-10-14
申请人： Shigeru Morokawa , Yasuhiro Takaki
发明人： Shigeru Morokawa , Yasuhiro Takaki
IPC分类号： G02F1/13 , G02B5/32 , G02B15/04 , G02F1/1335 , G02F1/139 , G02F1/29
CPC分类号： G02F1/29 , G02F1/13 , G02F1/1393 , G02F1/1396 , G02F2001/294 , G02F2203/28 , G02F2203/50
摘要： A liquid crystal active lens having, in combination, a fixed-focal-point lens having a high index of refraction and a phase modulation element comprising two-dimensionally arranged fine pixels, and having power and being capable of electrically controlling the lens characteristics as a function of space. An electrically controlled optical system can be realized without having a moving portion. Owing to the combination of the liquid crystal element for modulating space phase and the high-power lens of a fixed focal length, it is possible to electronically control the focal length and to electronically control the lens in a spatially split manner.
摘要翻译：一种液晶有源透镜，其组合具有高折射率的固定焦点透镜和包括二维排列的精细像素的相位调制元件，并具有电力并且能够将透镜特性电控制为空间功能可以实现电控光学系统而不具有移动部分。由于用于调制空间相位的液晶元件和固定焦距的高倍镜头的组合，可以电子地控制焦距并以空间分割方式电子地控制透镜。

3. 发明授权

US4433920A Electronic timepiece having improved primary frequency divider response characteristics 失效
标题翻译：具有改进的主分频器响应特性的电子钟表
公开(公告)号：US4433920A
公开(公告)日：1984-02-28
申请号：US281251
申请日：1981-07-07
申请人： Fukuo Sekiya , Shigeru Morokawa , Ryoji Iwakura
发明人： Fukuo Sekiya , Shigeru Morokawa , Ryoji Iwakura
IPC分类号： G04G3/02 , G04G19/06 , H03K23/40 , G04B17/12
CPC分类号： G04G3/02 , G04G19/06 , H03K23/40
摘要： In an electronic timepiece having a primary frequency divider circuit coupled to receive a standard frequency signal and comprising a group of P-channel FETs and a group of N-channel FETs, a bias circuit supplies a bias input to the P-channel FET group and a separate bias input to the N-channel FET group. By providing these bias inputs through current mirror coupling from a standard current source, the response of the primary frequency divider circuit to low amplitudes of the standard frequency signal can be made substantially independent of timepiece battery voltage variations, over a wide range of battery voltages.
摘要翻译：在具有耦合以接收标准频率信号并包括一组P沟道FET和一组N沟道FET的主分频器电路的电子钟表中，偏置电路将偏置输入提供给P沟道FET组，并且一个单独的偏置输入到N沟道FET组。通过通过来自标准电流源的电流镜耦合提供这些偏置输入，可以在宽范围的电池电压下使主分频器电路对标准频率信号的低振幅的响应基本上与时钟电池电压变化无关。

4. 发明授权

US4234945A Electronic timepiece with hourly strike mechanism 失效
标题翻译：电子钟表，具有小时冲击机制
公开(公告)号：US4234945A
公开(公告)日：1980-11-18
申请号：US883897
申请日：1978-03-06
申请人： Yasushi Nomura , Yuzo Komatsu , Shigeru Morokawa
发明人： Yasushi Nomura , Yuzo Komatsu , Shigeru Morokawa
IPC分类号： G04B21/10 , G04C21/12 , G04G13/00 , G04B21/00 , G04B21/02 , G08B3/00
CPC分类号： G04B21/10 , G04G13/00
摘要： An electronic timepiece having an acoustic hour information function in which a photosensitive switch mechanism essentially comprising a photosensitive element is provided to detect a quantity of light below a predetermined value in the surrounding environment where the timepiece is placed and control the acoustic hour information function of the timepiece depending upon the detected result.
摘要翻译：一种具有声学小时信息功能的电子钟表，其中设置了基本上包括感光元件的感光开关机构，以便在放置钟表的周围环境中检测低于预定值的光量，并且控制声学时间信息功能时钟取决于检测结果。

5. 发明授权

US4205518A Voltage conversion system for electronic timepiece 失效
标题翻译：电子表的电压转换系统
公开(公告)号：US4205518A
公开(公告)日：1980-06-03
申请号：US912268
申请日：1978-06-05
申请人： Shigeru Morokawa
发明人： Shigeru Morokawa
IPC分类号： G04G19/04 , H02M3/07 , G04C3/00
CPC分类号： H02M3/07 , G04G19/04
摘要： A voltage conversion system for an electronic timepiece having a power source, which system generates power at lower voltage level than that of the power source for operating at least one of a frequency standard, a frequency converter, a time counter circuit and a display system. The voltage conversion system comprises an oscillator circuit coupled to the power source to generate output signals, a plurality of capacitors, and a plurality of switching elements responsive to the output signals for alternately setting the capacitors in a parallel connected condition and a series connected condition, whereby an output voltage lower than that of the power source is generated at an output terminal of the system.
摘要翻译：一种具有电源的电子时钟的电压转换系统，该系统产生比用于操作频率标准，频率转换器，时间计数器电路和显示系统中的至少一个的电源的低电压电平的电力。电压转换系统包括耦合到电源以产生输出信号的振荡器电路，多个电容器和响应于输出信号的多个开关元件，用于交替地将电容器设置为并联连接状态和串联连接状态，从而在系统的输出端产生低于电源的输出电压。

6. 发明授权

US4199699A Motor and drive for a timepiece 失效
标题翻译：电机和驱动器的钟表
公开(公告)号：US4199699A
公开(公告)日：1980-04-22
申请号：US639987
申请日：1975-12-11
申请人： Kazunari Kume , Minoru Watanabe , Hideshi Ohno , Munetaka Tamaru , Takayasu Machida , Seiichi Nakamura , Shigeru Morokawa
发明人： Kazunari Kume , Minoru Watanabe , Hideshi Ohno , Munetaka Tamaru , Takayasu Machida , Seiichi Nakamura , Shigeru Morokawa
IPC分类号： G04C3/14 , F16H27/04 , G04C3/00 , G04C9/00 , H02K7/116 , H02K37/16 , H02K37/00
CPC分类号： G04C3/008 , F16H27/045 , G04C9/00 , H02K7/1166
摘要： An electronic timepiece including a battery, a drive motor, a drive, a display, and electronic circuits for driving said motor. The motor is a pulse motor and comprises a core, coil, yoke and rotor. The rotor includes a worm gear having worm teeth which engage with a gear wheel. The teeth on the worm gear are arranged and configured such that the initial and final portions of each tooth which engage with the gear wheel are parallel to the plane of rotation of the rotor thereby preventing torque applied to the gear wheel from being transmitted to the rotor.
摘要翻译：包括电池，驱动电动机，驱动器，显示器和用于驱动所述电动机的电子电路的电子钟表。电机是脉冲电机，包括铁芯，线圈，磁轭和转子。转子包括具有与齿轮啮合的蜗轮的蜗轮。蜗轮上的齿被布置和构造成使得与齿轮接合的每个齿的初始和最终部分平行于转子的旋转平面，从而防止施加到齿轮的扭矩传递到转子。

7. 发明授权

US4058969A Electric timepiece for displaying the operating condition thereof 失效
标题翻译：电表用于显示其工作状态
公开(公告)号：US4058969A
公开(公告)日：1977-11-22
申请号：US721439
申请日：1976-09-08
申请人： Munetaka Tamaru , Kazunari Kume , Hideshi Oono , Minoru Watanabe , Hideo Sato , Shigeru Morokawa
发明人： Munetaka Tamaru , Kazunari Kume , Hideshi Oono , Minoru Watanabe , Hideo Sato , Shigeru Morokawa
IPC分类号： G04C10/04 , G04G9/00 , G04C3/00
CPC分类号： G04C10/04 , G04G9/00
摘要： In a battery operated an electric timepiece operated by a battery of the type a time display, such as a second hand, when the voltage of the battery decreases below a predetermined value, the movement of the second hand is modified to give an alarm that the life of the battery has terminated.
摘要翻译：在电池操作的电池中，由例如秒针的时间显示类型的电池操作的电子计时器，当电池的电压降低到预定值以下时，修改了秒针的移动，发出报警，电池的使用寿命终止了。

8. 发明授权

US4045692A Solid state binary logic signal source for electronic timepiece or the like 失效
标题翻译：用于电子定时或类似的固态二进制逻辑信号源
公开(公告)号：US4045692A
公开(公告)日：1977-08-30
申请号：US615850
申请日：1975-09-23
申请人： Shigeru Morokawa , Fukuo Sekiya
发明人： Shigeru Morokawa , Fukuo Sekiya
IPC分类号： G04F5/00 , G04G5/02 , G04G21/00 , G04G99/00 , H03K5/02 , H03K17/00 , H03K19/0944 , H03K3/353 , G04C3/00 , H03K3/286 , H03K17/04
CPC分类号： G04F5/00 , G04G5/02 , H03K5/023
摘要： An inverting amplifier is provided with a high impedance input resistor connected at one end to an input terminal of the amplifier and connected at the other end to a first voltage source constituting a first binary logic level. The input terminal is also connected through a switch to a second voltage source constituting a second and opposite binary level. An MOS-FET has source and drain electrodes connected to the input terminal and the first voltage source respectively and a gate electrode connected to an output terminal of the amplifier. When the switch is closed, the second voltage is applied to the input terminal and the inverted output of the amplifier turns off the MOS-FET. When the switch is open, the first voltage is applied to the input terminal through the resistor and the inverted output of the amplifier turns on the MOS-FET. The low impedance of the MOS-FET in the turned on condition increases the stability of the amplifier under high humidity conditions.

9. 发明授权

US4016476A Booster circuits 失效
标题翻译：加速电路
公开(公告)号：US4016476A
公开(公告)日：1977-04-05
申请号：US630811
申请日：1975-11-11
申请人： Shigeru Morokawa , Fukuo Sekiya
发明人： Shigeru Morokawa , Fukuo Sekiya
IPC分类号： G04G19/04 , G04G19/08 , H02M3/07 , H03K5/003 , H03K5/02 , H03K19/0185 , H03K19/094 , H02M7/00
CPC分类号： H03K19/018507 , G04G19/04 , G04G19/08 , H02M3/07 , H03K19/094 , H03K5/003 , H03K5/023
摘要： An input line carrying a square-wave voltage is connected through a capacitor to the drain and via an inverter to the gate of a MOSFET acting as a diode, the relative magnitudes of the drain and gate pulses being so chosen that the FET conducts during alternate half-cycles of the square wave whereby the capacitor is charged during nonconductive half-cycles and is fully discharged to the potential of the source of the FET during conductive half-cycles. If the source is biased by a constant voltage, a square wave in a higher voltage range is available at the drain. If the source is connected to potential through another capacitance, a d-c voltage is available at that electrode. Complementary MOSFET/diodes can be connected in push-pull or in cascade to amplify the input voltage; they may also be combined with supplementary voltage boosters including cascaded stages composed of ordinary diodes and capacitors. The MOSFET/diode may be part of an electronic clock drive.
摘要翻译：承载方波电压的输入线通过电容器连接到漏极，并且通过反相器连接到用作二极管的MOSFET的栅极，所以选择漏极和栅极脉冲的相对幅度，使得FET在交替期间导通方波的半周期，由此电容器在非导通半周期期间被充电，并且在导电半周期期间完全放电到FET源极的电位。如果源被恒定电压偏置，则在漏极处可获得较高电压范围内的方波。如果源极通过另一个电容连接到电位，那么在该电极处可以获得d-c电压。互补MOSFET /二极管可以以推挽或级联方式连接，以放大输入电压; 它们还可以与包括由普通二极管和电容器组成的级联级的辅助升压器组合。 MOSFET /二极管可能是电子时钟驱动器的一部分。

10. 发明授权

US4015419A Electronic timepiece 失效
标题翻译：电子钟表
公开(公告)号：US4015419A
公开(公告)日：1977-04-05
申请号：US658037
申请日：1976-02-13
申请人： Shigeru Morokawa , Yukio Hashimoto
发明人： Shigeru Morokawa , Yukio Hashimoto
IPC分类号： G04F5/06 , G04G3/02 , G06F7/68 , G04C3/00
CPC分类号： G04F5/06 , G04G3/022 , G06F7/68
摘要： To facilitate acceleration or deceleration of the stepping rate of a time-keeping counter responding to driving pulses from a frequency divider connected to a crystal-controlled oscillator, a succession of such driving pulses is taken from an OR gate with inputs receiving a basic pulse train .phi..sub..gamma. a normally present first ancillary pulse train .phi..sub..beta. spacedly interleaved with pulse train .phi..sub..gamma. and a normally absent second ancillary pulse train .phi..sub..alpha. with pulse positions offset from those of the other two pulse trains. To retard the timepiece, the pulses of train .phi..sub..beta. are blocked for a desired period; to advance it, pulses of train .phi..sub..alpha. are interpolated at a rate depending on the cadence of a series of control pulses selectively synthesized from a combination of low-frequency stage outputs of the frequency divider. Externally set selection signals are temporarily stored in a memory circuit including NOR gates with positive-feedback connections to inverting inputs thereof, the memory circuit being periodically tested by a resetting pulse recurring at a frequency lower than that of the driving pulses.
摘要翻译：为了便于对来自连接到晶体振荡器的分频器的驱动脉冲响应的计时器的步进速度的加速或减速，从OR门获取一系列这样的驱动脉冲，其中输入接收基本脉冲串 phiγ是与脉冲串phiγ间隔地交错的正常存在的第一辅助脉冲串phiβ和具有与其他两个脉冲序列的脉冲位置偏移的脉冲位置的正常缺少的第二辅助脉冲串phiα。为了延迟时计，火车phi beta的脉冲被阻挡一段期望的时间; 为了使其前进，列车速率α的脉冲以取决于从分频器的低频级输出的组合选择合成的一系列控制脉冲的频率的速率内插。外部选择信号被临时存储在包括具有与其反相输入端的正反馈连接的NOR门的存储器电路中，存储器电路通过以低于驱动脉冲的频率重复的复位脉冲周期性地测试。

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