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1. 发明授权

US4638497A Framing code detector for a teletext receiver 失效
标题翻译：图文电视接收机的成帧检测器
公开(公告)号：US4638497A
公开(公告)日：1987-01-20
申请号：US653524
申请日：1984-09-24
申请人： Shigeru Komatsu , Keiji Kawata
发明人： Shigeru Komatsu , Keiji Kawata
IPC分类号： H04N7/025 , H04L7/04 , H04N7/03 , H04N7/035 , H04L7/08 , H04J3/06 , H04N1/36
CPC分类号： H04L7/042 , H04N7/035 , H04L7/046
摘要： A framing code detector includes a shift register supplied with a received framing code and a number of EX-OR gates each having one input connected to a respective stage of the shift register and another input which is supplied with a respective bit of a stored pattern having the inverted form of the anticipated framing code to be received/ a counter is provided for counting the number of times all outputs of EX-OR gates become "1" during a predetermined period, and an identification signal is produced when the count value of the counter is greater than a predetermined value.
摘要翻译：成帧代码检测器包括一个移位寄存器，该移位寄存器被提供有接收到的成帧代码和多个异或门，每个异或门具有连接到移位寄存器的各个级的一个输入端，另一个输入端被提供有存储模式的相应位，提供要接收的预期成帧代码的反转形式/计数器，用于在预定时间段期间对EX-OR门的所有输出的数量变为“1”的次数进行计数，并且当计数器的计数值计数器大于预定值。

2. 发明申请

US20080218628A1 Decoder Device And Receiver Using The Same 有权
标题翻译：解码器和接收器使用它
公开(公告)号：US20080218628A1
公开(公告)日：2008-09-11
申请号：US12120472
申请日：2008-05-14
申请人： Masuo Oku , Hironori Komi , Keisuke Inata , Ryosuke Toya , Kenji Katsumata , Shigeru Komatsu , Shinobu Torikoshi , Takaaki Matono , Fumihito Tanaka , Masaaki Hisanaga
发明人： Masuo Oku , Hironori Komi , Keisuke Inata , Ryosuke Toya , Kenji Katsumata , Shigeru Komatsu , Shinobu Torikoshi , Takaaki Matono , Fumihito Tanaka , Masaaki Hisanaga
IPC分类号： H04N7/01
CPC分类号： H04N5/775 , H04N5/4401 , H04N5/445 , H04N5/45 , H04N5/46 , H04N5/85 , H04N7/012 , H04N21/42638 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/440218
摘要： A decoder apparatus which includes a de-multiplexer, which is configured to divide motion picture data from a transport stream, a video decoder, which is configured to decode the divided motion picture data, and a first re-formatter on-screen unit, which is configured to display motion picture data and at least one of first and second graphic data on a screen. The first re-formatter on-screen unit converts motion picture data of a first aspect ratio, which is decoded by the video decoder, and first graphics data, which is produced by applying information relating to a caption corresponding to the motion picture data, into a second aspect ratio, when outputting the motion picture data of the first aspect ratio after conversion into the second aspect ratio, without converting the aspect ratio of second graphic data, which is produced by applying information relating to a program guide.
摘要翻译：一种解码器装置，包括解复用器，其被配置为从传输流分割运动图像数据，被配置为对分割的运动图像数据进行解码的视频解码器和第一重新格式化器屏幕单元，其中被配置为在屏幕上显示运动图像数据和第一和第二图形数据中的至少一个。第一重新格式化器屏幕单元将由视频解码器解码的第一宽高比的运动图像数据和通过将与运动图像数据相对应的字幕相关的信息应用的信息产生的第一图形数据转换成第二宽高比，当在转换成第二宽高比之后输出第一宽高比的运动图像数据而不转换通过应用与节目指南相关的信息而产生的第二图形数据的纵横比。

3. 发明授权

US06710817B2 Decoder device and receiver using the same 有权
标题翻译：解码器和接收机使用相同
公开(公告)号：US06710817B2
公开(公告)日：2004-03-23
申请号：US09984508
申请日：2001-10-30
申请人： Masuo Oku , Hironori Komi , Keisuke Inata , Ryosuke Toya , Kenji Katsumata , Shigeru Komatsu , Shinobu Torikoshi , Takaaki Matono , Fumihito Tanaka , Masaaki Hisanaga
发明人： Masuo Oku , Hironori Komi , Keisuke Inata , Ryosuke Toya , Kenji Katsumata , Shigeru Komatsu , Shinobu Torikoshi , Takaaki Matono , Fumihito Tanaka , Masaaki Hisanaga
IPC分类号： H04N550
CPC分类号： H04N5/775 , H04N5/4401 , H04N5/445 , H04N5/45 , H04N5/46 , H04N5/85 , H04N7/012 , H04N21/42638 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/440218
摘要： An object of the present application is to provide the display of motion picture data used in both of analog and digital broadcasts with high picture quality and a common user interface. The above object can be achieved by providing a plurality of picture format converters, a plurality of OSD circuits, and means for storing motion picture data used in an analog broadcast in a common memory.
摘要翻译：本申请的目的是提供在具有高图像质量的模拟和数字广播两者中使用的运动图像数据的显示和公共用户界面。上述目的可以通过提供多个图像格式转换器，多个OSD电路和用于存储在公共存储器中的模拟广播中使用的运动图像数据的装置来实现。

4. 发明授权

US5179642A Image synthesizing apparatus for superposing a second image on a first image 失效
标题翻译：用于将第二图像叠加在第一图像上的图像合成装置
公开(公告)号：US5179642A
公开(公告)日：1993-01-12
申请号：US856827
申请日：1992-03-25
申请人： Shigeru Komatsu
发明人： Shigeru Komatsu
IPC分类号： G06T15/40
CPC分类号： G06T15/40
摘要： An image synthesizing apparatus for synthesizing first and second images with each other which includes a first display memory for storing a first image data constituting a first image, and a display memory control device for comparing a second image data for constituting a second image with a predetermined image data to thereby judge whether the second image data is to be written into the first display memory or not.
摘要翻译：一种用于合成第一和第二图像的图像合成装置，包括：第一显示存储器，用于存储构成第一图像的第一图像数据;以及显示存储器控制装置，用于将用于构成第二图像的第二图像数据与预定的从而判断第二图像数据是否被写入第一显示存储器。

5. 发明授权

US4980765A Frame buffer memory for display 失效
标题翻译：帧缓冲存储器用于显示
公开(公告)号：US4980765A
公开(公告)日：1990-12-25
申请号：US464214
申请日：1990-01-12
申请人： Yoshimichi Kudo , Shigeru Komatsu
发明人： Yoshimichi Kudo , Shigeru Komatsu
IPC分类号： G09G5/00 , G06F12/02 , G06T1/60 , G09G5/14 , G09G5/34 , G09G5/39 , G09G5/397
CPC分类号： G09G5/14 , G09G5/397 , G09G2360/126
摘要： A frame buffer memory capable of storing video data for plural frames of pictures with memory areas irrelevant to the display being reduced to a minimum, which video data consist of a number of pixels unequal to a power of "2" in the vertical and horizontal directions, respectively. The frame buffer memory is realized by using multi-port video RAMs and includes a plurality of regions for display and auxiliary regions. The regions for display includes at least first and second display regions which partially overlap each other. The auxiliary regions store the video data contained in the overlapping portion (overlapping region) of the first and second display regions, the video data stored in the auxiliary region being transferred to the overlapping region as occasion requires.
摘要翻译：能够将与图像无关的存储区域的多帧图像的视频数据的帧缓冲存储器减少到最小，哪个视频数据由不同于垂直和水平方向上的“2”的功率的像素数组成，分别。帧缓冲存储器是通过使用多端口视频RAM来实现的，并且包括用于显示和辅助区域的多个区域。用于显示的区域至少包括彼此部分重叠的至少第一和第二显示区域。辅助区域存储包含在第一和第二显示区域的重叠部分（重叠区域）中的视频数据，根据需要，存储在辅助区域中的视频数据被传送到重叠区域。

6. 发明授权

US4692190A Trimming of metal interconnection layer by selective migration of metal atoms by energy beams 失效
标题翻译：通过能量束选择性迁移金属原子来修剪金属互连层
公开(公告)号：US4692190A
公开(公告)日：1987-09-08
申请号：US813039
申请日：1985-12-24
申请人： Shigeru Komatsu
发明人： Shigeru Komatsu
IPC分类号： H01L21/3205 , H01L21/268 , H01L21/82 , H01L23/525 , H01C7/00 , B23K26/00
CPC分类号： H01L23/525 , H01L21/268 , H01L2924/0002 , Y10S148/093 , Y10S148/14
摘要： Semiconductor body is prepared and a film is formed on the semiconductor body, followed by forming an interconnection layer of aluminum alloy on the insulating film. A silicon oxide film is formed on the interconnection layer, followed by removing that portion of the silicon oxide film which is situated on a predetermined trimming area of the interconnection layer. A silicon nitride film is formed on the whole surface of the resultant structure. An energy beam is directed onto the predetermined trimming area of the interconnection layer, causing the interconnection layer to be locally heated to 400.degree. to 600.degree. C. whereby atoms in the interconnection layer migrate to permit the interconnection layer to be trimmed.
摘要翻译：制备半导体体，在半导体体上形成膜，然后在绝缘膜上形成铝合金的配线层。在互连层上形成氧化硅膜，然后除去位于互连层的预定修整区域上的部分氧化硅膜。在所得结构的整个表面上形成氮化硅膜。能量束被引导到互连层的预定修整区域上，使得互连层局部加热至400℃至600℃，由此互连层中的原子迁移以允许互连层被修整。

7. 发明授权

US4484212A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4484212A
公开(公告)日：1984-11-20
申请号：US335712
申请日：1981-12-29
申请人： Shigeru Komatsu , Michio Nakamura , Katsuji Fujita
发明人： Shigeru Komatsu , Michio Nakamura , Katsuji Fujita
IPC分类号： H01L27/04 , H01L21/768 , H01L21/822 , H01L23/522 , H01L23/58 , H01L27/08 , H01L29/84 , H01L23/48 , H01L27/02 , H01L29/44
CPC分类号： H01L23/585 , H01L23/522 , H01L27/0802 , H01L2924/0002 , Y10S257/925 , Y10S73/04
摘要： A semiconductor device comprising a semiconductor substrate having at least two resistor elements, wherein said resistor elements have a specific resistance ratio relative to each other, an insulation layer formed on a major surface of said semiconductor substrate, a circuit wiring layer formed on said insulation layer covering a portion of said insulation layer which corresponds to at least one of said resistor elements, and a dummy wiring layer made of the same material as that of the circuit wiring layer and formed on the insulation layer covering that portion of said insulation layer which corresponds to the resistor element or elements not covered by said circuit wiring layer, and where the ratio of an overlapping area of one resistor element in said circuit wiring layer and an overlapping area of the other resistor element and said dummy wiring layer is equal to a resistance ratio of said resistor elements.
摘要翻译：一种半导体器件，包括具有至少两个电阻元件的半导体衬底，其中所述电阻元件相对于彼此具有比电阻比，形成在所述半导体衬底的主表面上的绝缘层，形成在所述绝缘层上的电路布线层覆盖对应于所述电阻元件中的至少一个的所述绝缘层的一部分，以及由与所述电路布线层相同的材料制成的虚拟布线层，并形成在所述绝缘层上，覆盖所述绝缘层对应的部分连接到所述电路布线层未被覆盖的电阻元件或元件，并且其中所述电路布线层中的一个电阻元件的重叠区域与所述另一个电阻元件与所述伪布线层的重叠区域的重叠面积之比等于电阻所述电阻元件的比例。

8. 发明授权

US4451844A Polysilicon emitter and base contacts separated by lightly doped poly separator 失效
标题翻译：多晶硅发射极和基极触点由轻掺杂的多分离器分离
公开(公告)号：US4451844A
公开(公告)日：1984-05-29
申请号：US289961
申请日：1981-08-04
申请人： Shigeru Komatsu , Michio Nakamura
发明人： Shigeru Komatsu , Michio Nakamura
IPC分类号： H01L29/73 , H01L21/285 , H01L21/331 , H01L27/06 , H01L29/417 , H01L29/45 , H01L23/50 , H01L23/52
CPC分类号： H01L21/28525 , H01L27/06 , H01L29/417 , H01L29/456
摘要： A semiconductor device comprising a semiconductor substrate of an N conductivity type; an insulation layer of a predetermined pattern for selectively covering the substrate; a first region of a P conductivity type formed in that area of the substrate which is surrounded by the insulation layer; a second region of the P.sup.+ conductivity type having a high impurity concentration and formed in the first region; a third region of the N conductivity type formed in the first region; a polycrystalline silicon layer formed on the major surface of the substrate, said polycrystalline silicon layer comprising a first portion of the P conductivity type contacting the second region, a second portion of the N conductivity type contacting the third region and a third portion contacting the first region, said first and second portions constituting first and second contacting electrodes, respectively, and the third portion having a predetermined impurity concentration and constituting a separation portion for insulating the first and second portions from each other.
摘要翻译：一种半导体器件，包括N导电类型的半导体衬底; 用于选择性地覆盖衬底的预定图案的绝缘层; 形成在由绝缘层包围的基板的该区域中的P导电型的第一区域; 形成在第一区域中的具有高杂质浓度的P +导电型的第二区域; 形成在第一区域中的N导电类型的第三区域; 形成在所述基板的主表面上的多晶硅层，所述多晶硅层包括接触所述第二区域的P导电类型的第一部分，与所述第三区域接触的所述N导电类型的第二部分和接触所述第一区域的第三部分所述第一和第二部分分别构成第一和第二接触电极，第三部分具有预定的杂质浓度，并构成用于使第一和第二部分彼此绝缘的分离部分。

9. 发明授权

US4388707A Memory selecting system 失效
标题翻译：内存选择系统
公开(公告)号：US4388707A
公开(公告)日：1983-06-14
申请号：US279071
申请日：1981-06-30
申请人： Shigeru Komatsu , Kazushi Mizukami , Tsuguji Tachiuchi , Kunihiko Nagai , Takuo Koyama
发明人： Shigeru Komatsu , Kazushi Mizukami , Tsuguji Tachiuchi , Kunihiko Nagai , Takuo Koyama
IPC分类号： G06F12/00 , G06F12/06 , G11C8/12 , G11C8/00
CPC分类号： G11C8/12 , G06F12/0623
摘要： A memory selection system which facilitates the addition of an external memory to a digital processing unit having an internal memory is disclosed. When a plurality of memories have the same addresses and an overlapped address is accessed, priority among the memories having the overlapped address is discriminated to enable only the memory having the highest priority (last attached memory) to be selected for access and to disable the access of the other memories.
摘要翻译：公开了一种便于将外部存储器添加到具有内部存储器的数字处理单元的存储器选择系统。当多个存储器具有相同的地址并且重叠地址被访问时，区分具有重叠地址的存储器中的优先级，以使得仅能够选择具有最高优先级的存储器（最后附加存储器）以进行访问并禁用访问的其他记忆。

10. 发明授权

US07643089B2 Decoder device and receiver using the same 有权
标题翻译：解码器和接收机使用相同
公开(公告)号：US07643089B2
公开(公告)日：2010-01-05
申请号：US12120472
申请日：2008-05-14
申请人： Masuo Oku , Hironori Komi , Keisuke Inata , Ryosuke Toya , Kenji Katsumata , Shigeru Komatsu , Shinobu Torikoshi , Takaaki Matono , Fumihito Tanaka , Masaaki Hisanaga
发明人： Masuo Oku , Hironori Komi , Keisuke Inata , Ryosuke Toya , Kenji Katsumata , Shigeru Komatsu , Shinobu Torikoshi , Takaaki Matono , Fumihito Tanaka , Masaaki Hisanaga
IPC分类号： H04N11/20 , H04N5/45
CPC分类号： H04N5/775 , H04N5/4401 , H04N5/445 , H04N5/45 , H04N5/46 , H04N5/85 , H04N7/012 , H04N21/42638 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/440218
摘要： A decoder apparatus which includes a de-multiplexer, which is configured to divide motion picture data from a transport stream, a video decoder, which is configured to decode the divided motion picture data, and a first re-formatter on-screen unit, which is configured to display motion picture data and at least one of first and second graphic data on a screen. The first re-formatter on-screen unit converts motion picture data of a first aspect ratio, which is decoded by the video decoder, and first graphics data, which is produced by applying information relating to a caption corresponding to the motion picture data, into a second aspect ratio, when outputting the motion picture data of the first aspect ratio after conversion into the second aspect ratio, without converting the aspect ratio of second graphic data, which is produced by applying information relating to a program guide.
摘要翻译：一种解码器装置，包括解复用器，其被配置为从传输流分割运动图像数据，被配置为对分割的运动图像数据进行解码的视频解码器和第一重新格式化器屏幕单元，其中被配置为在屏幕上显示运动图像数据和第一和第二图形数据中的至少一个。第一重新格式化器屏幕单元将由视频解码器解码的第一宽高比的运动图像数据和通过将与运动图像数据相对应的字幕相关的信息应用的信息产生的第一图形数据转换成第二宽高比，当在转换成第二宽高比之后输出第一宽高比的运动图像数据而不转换通过应用与节目指南相关的信息而产生的第二图形数据的纵横比。

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