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1. 发明授权

US5321654A Semiconductor device having no through current flow in standby period 失效
标题翻译：半导体器件在待机期间没有通过电流流动
公开(公告)号：US5321654A
公开(公告)日：1994-06-14
申请号：US863975
申请日：1992-04-06
申请人： Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Mori , Shigeru Kikuda , Makoto Suwa , Mitsuya Kinoshita
发明人： Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Mori , Shigeru Kikuda , Makoto Suwa , Mitsuya Kinoshita
IPC分类号： G11C11/408 , G11C5/14 , G11C7/22 , G11C8/18 , G11C11/401 , G11C11/409 , H01L21/822 , H01L27/04 , H01L27/10 , G11C7/00
CPC分类号： G11C7/22 , G11C5/14 , G11C8/18
摘要： A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.
摘要翻译：一种具有放大电路的半导体器件，该放大电路设置在相应的接合焊盘附近，接收外部信号，并且位于接合焊盘和要施加这样的外部信号的内部电路之间。该装置包括用于放大电路的控制信号发生电路，其不在常规半导体器件中提供。响应于外部控制信号，控制信号发生电路产生用于控制放大电路中的电源和接地之间的电气路径的内部控制信号。在半导体器件的待机期间，电源和接地之间的路径被切断，而不管相应的焊盘的电位如何，防止通过电流的流动。

2. 发明授权

US5357478A Semiconductor integrated circuit device including a plurality of cell array blocks 失效
标题翻译：包括多个单元阵列块的半导体集成电路装置
公开(公告)号：US5357478A
公开(公告)日：1994-10-18
申请号：US767332
申请日：1991-09-30
申请人： Shigeru Kikuda , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Makoto Suwa , Mitsuya Kinoshita
发明人： Shigeru Kikuda , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Makoto Suwa , Mitsuya Kinoshita
IPC分类号： H01L21/822 , G11C5/02 , G11C11/401 , H01L27/04 , H01L27/10 , G11C8/00
CPC分类号： G11C5/025
摘要： A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.
摘要翻译：在芯片上形成多个子芯片。输入/输出缓冲区布置在多个子芯片周围。每个子芯片包括子芯片控制电路区域和多个存储单元阵列块。每个存储单元阵列块包括存储单元阵列区域，行解码器和控制电路区域，读出放大器区域和输入/输出锁存区域。

3. 发明授权

US5323348A Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit 失效
标题翻译：具有多个存储器阵列并且包括用于修复故障位的冗余电路的半导体存储器件
公开(公告)号：US5323348A
公开(公告)日：1994-06-21
申请号：US767316
申请日：1991-09-30
申请人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
发明人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
IPC分类号： G11C11/401 , G11C11/409 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/848
摘要： Column repairing circuits 7a, 7b for repairing a DRAM in which there are defective memory cells in two columns are disclosed. The connection state of switching elements or circuits 51-5n, 61-6n, 71-7 (n+1), 81-8 (n+1) is determined as illustrated by appropriately disconnecting fuses in fuse links provided respectively in circuits 7a, 7b. Accordingly, column selecting lines Y2a and Y (n+1) b in memory array blocks 891a, 891b are not activated. The two repairing circuits 7a, 7b are provided spaced apart from each other on a semiconductor substrate, so that excessive concentration of fuse elements and switching elements or circuits is prevented.
摘要翻译：公开了用于修复其中存在两列不良存储器单元的DRAM的列修复电路7a，7b。开关元件或电路51-5n，61-6n，71-7（n + 1），81-8（n + 1）的连接状态通过适当地断开分别设置在电路7a， 7b。因此，存储器阵列块891a，891b中的列选择线Y2a和Y（n + 1）b未被激活。两个修复电路7a，7b在半导体衬底上彼此间隔开设置，从而防止了熔丝元件和开关元件或电路的过度集中。

4. 发明授权

US5574729A Redundancy circuit for repairing defective bits in semiconductor memory device 失效
标题翻译：用于修复半导体存储器件中的有缺陷的位的冗余电路
公开(公告)号：US5574729A
公开(公告)日：1996-11-12
申请号：US338817
申请日：1994-11-10
申请人： Mitsuya Kinoshita , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Shigeru Kikuda , Makoto Suwa
发明人： Mitsuya Kinoshita , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Shigeru Kikuda , Makoto Suwa
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G06F11/00
CPC分类号： G11C29/848
摘要： A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.
摘要翻译：一种半导体存储器件包括多个存储块，i个在多个存储块上延伸的主行或列选择线，以及用于根据所施加的地址信号选择主行或列选择线中的一个的解码器。解码器包括i个输出。每个存储块包括排列成行和列的多个存储器单元和至少（i + 1）个子行或列选择线，每个用于选择一行或一列存储单元。为每个存储块提供移位冗余电路，用于连接主行或列选择线和子行或列选择线。移位冗余电路包括用于将一个主行或列选择线连接到多个相邻子行或列选择线中的一个的开关电路和用于设置开关电路的连接路径的电路。除了与有缺陷的位相关联的有缺陷的子行或列选择线之外，移位冗余电路将连续相邻的子行或列选择线以一对一的对应方式连接到主行或列选择线。

5. 发明授权

US5384784A Semiconductor memory device comprising a test circuit and a method of operation thereof 失效
标题翻译：半导体存储器件，包括测试电路及其操作方法
公开(公告)号：US5384784A
公开(公告)日：1995-01-24
申请号：US750040
申请日：1991-08-27
申请人： Shigeru Mori , Makoto Suwa , Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Kikuda , Mitsuya Kinoshita
发明人： Shigeru Mori , Makoto Suwa , Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Kikuda , Mitsuya Kinoshita
IPC分类号： G11C11/409 , G11C11/401 , G11C29/00 , G11C29/34 , G06F15/20
CPC分类号： G11C29/34
摘要： A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.
摘要翻译：半导体存储器件包括存储器阵列。存储器阵列中奇数次序的位线对属于第一组，偶数顺序的位线对属于第二组。第一放大器连接到每个位线对。对应于第一组，写总线读总线和读/测电路。对应于第二组，写总线读总线和读/测电路。列解码器在测试时同时选择多个位线对。在测试时，每个读/测试电路将从属于相应组的多个位线对中读出的数据与给定的预期数据进行比较，以提供比较结果。

6. 发明授权

US5337272A Circuit for applying selected voltages to dynamic random access memory 失效
标题翻译：将选定电压应用于动态随机存取存储器有效老化和存储单元测试的电路
公开(公告)号：US5337272A
公开(公告)日：1994-08-09
申请号：US32554
申请日：1993-03-17
申请人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
发明人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
IPC分类号： G11C11/404 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/50 , G11C11/40 , G11C11/407
CPC分类号： G11C29/50008 , G11C29/50 , G11C11/401
摘要： A dynamic random access memory (DRAM) includes a selection circuit for selecting the voltages used for aging. The selection circuit operates responsive to external control signals. When a source voltage (Vcc) is selected, the voltage (Vcc) is supplied to one electrode of a memory cell via a circuit 73 and a transmission gate while a ground potential (Vss) is supplied to the other electrode via a bit line and a transistor. Conversely, when the ground potential (Vss) is selected, an inverted voltage is applied across the two electrodes. In this manner, the insulating properties of an insulator interposed between the two electrodes can be checked more reliably during aging.
摘要翻译：动态随机存取存储器（DRAM）包括用于选择用于老化的电压的选择电路。选择电路响应于外部控制信号而工作。当选择源电压（Vcc）时，经由电路73和传输栅极将电压（Vcc）提供给存储单元的一个电极，同时通过位线将地电位（Vss）提供给另一电极，一个晶体管。相反，当选择接地电位（Vss）时，在两个电极之间施加反向电压。以这种方式，可以在老化期间更可靠地检查插入在两个电极之间的绝缘体的绝缘性。

7. 发明授权

US5079743A Circuit for applying selected voltages to dynamic random access memory 失效
标题翻译：将动作选择电压应用于动态随机存取存储器的电路
公开(公告)号：US5079743A
公开(公告)日：1992-01-07
申请号：US436587
申请日：1989-11-15
申请人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
发明人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
IPC分类号： G11C11/404 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/50
CPC分类号： G11C29/50008 , G11C29/50 , G11C11/401
摘要： A dynamic random access memory (DRAM) includes a selection circuit for selecting the voltages used for aging. The switching circuit operates responsive to external control signals. When a source voltage (Vcc) is selected, the voltage (Vcc) is supplied to one electrode of a memory cell via a circuit 73 and a transmission gate while a ground potential (Vss) is supplied to the other electrode via a bit line and a transistor. Conversely, when the ground potential (Vss) is selected, an inverted voltage is applied across the two electrodes. In this manner, the insulating properties of an insulator interposed between the two electrodes can be checked more reliably during aging.
摘要翻译：动态随机存取存储器（DRAM）包括用于选择用于老化的电压的选择电路。开关电路响应于外部控制信号而工作。当选择源电压（Vcc）时，经由电路73和传输栅极将电压（Vcc）提供给存储单元的一个电极，同时通过位线将地电位（Vss）提供给另一电极，一个晶体管。相反，当选择接地电位（Vss）时，在两个电极之间施加反向电压。以这种方式，可以在老化期间更可靠地检查插入在两个电极之间的绝缘体的绝缘性。

8. 发明授权

US5146429A Semiconductor memory device including a redundancy circuitry for repairing a defective memory cell and a method for repairing a defective memory cell 失效
标题翻译：包括用于修复有缺陷的存储单元的冗余电路的半导体存储器件以及用于修复有缺陷的存储器单元的方法
公开(公告)号：US5146429A
公开(公告)日：1992-09-08
申请号：US617737
申请日：1990-11-26
申请人： Shinji Kawai , Shigeru Mori , Shigeru Kikuda
发明人： Shinji Kawai , Shigeru Mori , Shigeru Kikuda
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04
CPC分类号： G11C29/848
摘要： A semicondcutor memory device includes an array of a plurality of memory cells arranged in a matrix manner, and a row or column decoder responsive to an external address signal for generating a row or column selecting signal. The memory cell array comprises (n+1) rows or columns. The row or column decoder comprises n output nodes. Transmission gates are provided between the decoder output node and row lines or column selecting lines for connecting each output node and each row line or column selecting line. The transmission gates are formed of a pair of CMOS transmission gates, whereby one output node is connected to two adjacent row lines or column selecting lines. This memory device further includes a circuit defining the connection manner of the transmission gate. This defining circuit turns one pair of CMOS transmission gates ON and OFF complementally. When there is a defective memory cell, the decoder output nodes are grouped into a first group including the output node corresponding to the faulty row or column having the defective memory cell, and a second group formed of the remaining output nodes. The defining circuit applies control signals to the CMOS transmission gates so that the ON/OFF states of the CMOS transmission gate pair related to the first group of output nodes and the CMOS transmission gate pair related to the second group of output node differ. The memory device further includes switching devices provided corresponding to each row line or column selecting line, responsive to the control signal from the defining cirucit to be turned on/off. This switching device connects only the faulty row line or the faulty column selecting line to the reference potential fixedly.
摘要翻译：半切割器存储器件包括以矩阵方式布置的多个存储器单元的阵列，以及响应于用于产生行或列选择信号的外部地址信号的行或列解码器。存储单元阵列包括（n + 1）行或列。行或列解码器包括n个输出节点。在解码器输出节点和用于连接每个输出节点和每行行或列选择线的行线或列选择线之间提供传输门。传输门由一对CMOS传输门形成，其中一个输出节点连接到两个相邻的行线或列选择线。该存储装置还包括限定传输门的连接方式的电路。该定义电路互补地将一对CMOS传输门ON和OFF。当存在有缺陷的存储器单元时，解码器输出节点被分组为包括与具有缺陷存储单元的故障行或列相对应的输出节点的第一组，以及由剩余输出节点形成的第二组。定义电路将控制信号施加到CMOS传输门，使得与第一组输出节点相关的CMOS传输门对的ON / OFF状态和与第二组输出节点相关的CMOS传输门对不同。存储器件还包括响应于来自定义电路的控制信号而被打开/关闭而对应于每行行或列选择线提供的开关装置。该开关装置仅将故障行线或故障列选择线固定为参考电位。

9. 再颁专利

USRE35613E Dynamic random access memory with isolated well structure 失效
标题翻译：具有隔离井结构的动态随机存取存储器
公开(公告)号：USRE35613E
公开(公告)日：1997-09-23
申请号：US496569
申请日：1995-06-29
申请人： Kenichi Yasuda , Makoto Suwa , Shigeru Mori
发明人： Kenichi Yasuda , Makoto Suwa , Shigeru Mori
IPC分类号： H01L27/02 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10805 , H01L27/0218 , H01L27/105
摘要： A semiconductor memory device includes a first conductivity type well in a first conductivity type semiconductor substrate surrounded by a second conductivity type well, one of a memory cell and an external input circuit arranged on the first conductivity type well and the other disposed outside the second conductivity type well. A predetermined power supply voltage is applied to the second conductivity type well and the first conductivity type well is connected to ground. In the structure, charge carriers injected from the external input circuit are absorbed in the second conductivity type well. As a result, the charge carriers are prevented from reaching the memory cell and destroying data stored therein. Therefore, it is possible to miniaturize transistors and increase integration density of dynamic random access memory devices without degrading the source to drain dielectric strength.
摘要翻译：半导体存储器件包括第一导电类型的半导体衬底中的第一导电类型的阱，该第一导电类型的半导体衬底由第二导电类型阱围绕，存储单元和布置在第一导电类型阱上的外部输入电路之一，另一个位于第二导电类型类型很好。对第二导电类型阱施加预定的电源电压，并且将第一导电类型阱连接到地。在该结构中，从外部输入电路注入的电荷载流子被吸收在第二导电型阱中。结果，防止电荷载体到达存储单元并破坏其中存储的数据。因此，可以使晶体管小型化并提高动态随机存取存储器件的集成密度，而不会使源极降低介电强度。

10. 发明授权

US5281842A Dynamic random access memory with isolated well structure 失效
标题翻译：具有隔离井结构的动态随机存取存储器
公开(公告)号：US5281842A
公开(公告)日：1994-01-25
申请号：US722164
申请日：1991-06-27
申请人： Kenichi Yasuda , Makoto Suwa , Shigeru Mori
发明人： Kenichi Yasuda , Makoto Suwa , Shigeru Mori
IPC分类号： H01L27/02 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10805 , H01L27/0218 , H01L27/105
摘要： A semiconductor memory device includes a first conductivity type well in a first conductivity type semiconductor substrate surrounded by a second conductivity type well, one of a memory cell and an external input circuit arranged on the first conductivity type well and the other disposed outside the second conductivity type well. A predetermined power supply voltage is applied to the second conductivity type well and the first conductivity type well is connected to ground. In the structure, charge carriers injected from the external input circuit are absorbed in the second conductivity type well. As a result, the charge carriers are prevented from reaching the memory cell and destroying data stored therein. Therefore, it is possible to miniaturize transistors and increase integration density of dynamic random access memory devices without degrading the source to drain dielectric strength.
摘要翻译：半导体存储器件包括第一导电类型的半导体衬底中的第一导电类型的阱，该第一导电类型的半导体衬底由第二导电类型阱围绕，存储单元和布置在第一导电类型阱上的外部输入电路中的一个，类型很好。对第二导电类型阱施加预定的电源电压，并且将第一导电类型阱连接到地。在该结构中，从外部输入电路注入的电荷载流子被吸收在第二导电型阱中。结果，防止电荷载体到达存储单元并破坏其中存储的数据。因此，可以使晶体管小型化并提高动态随机存取存储器件的集成密度，而不会使源极降低介电强度。

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