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1. 发明授权

US5561542A Optical communication system and method for performing communication under clock control 失效
标题翻译：用于在时钟控制下执行通信的光通信系统和方法
公开(公告)号：US5561542A
公开(公告)日：1996-10-01
申请号：US352746
申请日：1994-12-02
申请人： Masato Kosugi , Atsushi Date , Kazumasa Hamaguchi , Toshiyuki Fukui
发明人： Masato Kosugi , Atsushi Date , Kazumasa Hamaguchi , Toshiyuki Fukui
IPC分类号： H03G3/30 , H04B10/07 , H04B10/27 , H04B10/272 , H04J3/06 , H04L7/00 , H04B10/20 , H04J14/00
CPC分类号： H04J3/0682
摘要： In an optical communication system, a plurality of apparatuses are connected by a star coupler. A signal from each of the optical communication apparatuses is received by a receiving device such as a photodiode while a signal to each of the apparatuses is transmitted by a transmitting device such as a laser diode. A reference clock is supplied to the transmitting device. A clock of the signal from an optical communication apparatus is extracted to generate a phase comparison information signal of the extracted clock and the reference clock so as to supply the phase comparison information signal to the transmitting device. In the optical communication apparatus, a clock from the signal from the transmitting device is extracted, the phase comparison information signal contained in the signal from the transmitting device is extracted, and a transmit clock of the signal to be transmitted from the optical communication apparatus is controlled and oscillated such that a phase difference represented by the phase comparison signal is minimized.
摘要翻译：在光通信系统中，多个装置通过星形耦合器连接。来自每个光通信装置的信号由诸如光电二极管的接收装置接收，而到每个装置的信号由诸如激光二极管的发送装置发送。参考时钟提供给发送设备。提取来自光通信装置的信号的时钟以产生提取的时钟和参考时钟的相位比较信息信号，以便将相位比较信息信号提供给发送装置。在光通信装置中，提取来自发送装置的信号的时钟，提取包含在发送装置的信号中的相位比较信息信号，从光通信装置发送的信号的发送时钟为控制和振荡，使得由相位比较信号表示的相位差最小化。

2. 发明授权

US6009490A System having plurality of nodes with respective memories and an arbiter for performing arbitration of connection line use for transfer of data between nodes 失效
标题翻译：具有多个具有相应存储器的节点的系统和用于执行节点之间的数据传输的连接线路使用仲裁的仲裁器
公开(公告)号：US6009490A
公开(公告)日：1999-12-28
申请号：US915318
申请日：1997-08-20
申请人： Toshiyuki Fukui , Atsushi Date , Kazumasa Hamaguchi , Masato Kosugi
发明人： Toshiyuki Fukui , Atsushi Date , Kazumasa Hamaguchi , Masato Kosugi
IPC分类号： H04J1/00 , G06F13/362 , G06F13/38 , H04L12/44
CPC分类号： H04L12/44 , G06F13/362
摘要： An information processing apparatus has a plurality of nodes, a connection line for connection between the plurality of nodes, an arbiter for performing arbitration of use of the connection line, and an arbitration signal line for connection between the arbiter and each node, wherein the arbiter performs processing of a request for use of the connection line and processing of additional information related to data transfer executed after connection of the connection line. An arbitration method in the information processing apparatus includes steps of letting a node originating a request for use of the connection line, when requesting use of the connection line to the arbiter, also send additional information related to data transfer on the connection line together with the request for use to the arbiter; and letting the arbiter, when performing arbitration of use of the connection line to set the connection line based on the request, send the additional information related to the data transfer to a node being to receive the request.
摘要翻译：信息处理装置具有多个节点，用于多个节点之间的连接的连接线，用于执行连接线的使用仲裁的仲裁器以及仲裁器与每个节点之间的连接的仲裁信号线，其中仲裁器执行对连接线的使用请求的处理，以及处理与连接线连接之后执行的数据传输相关的附加信息。信息处理装置中的仲裁方法包括以下步骤：当请求使用连接线时，发出请求使用连接线的节点，同时在连接线上发送与数据传输有关的附加信息以及请求使用仲裁者; 并且在仲裁器根据该请求执行连接线的使用仲裁以设置连接线时，仲裁器将与数据传输有关的附加信息发送到要接收该请求的节点。

3. 发明授权

US5604748A Information processing apparatus for transmitting information among a plurality of nodes and arbitration method in such information processing apparatus 失效
标题翻译：用于在多个节点之间传送信息的信息处理装置和在这种信息处理装置中的仲裁方法
公开(公告)号：US5604748A
公开(公告)日：1997-02-18
申请号：US383184
申请日：1995-02-03
申请人： Atsushi Date , Kazumasa Hamaguchi , Masato Kosugi , Toshiyuki Fukui
发明人： Atsushi Date , Kazumasa Hamaguchi , Masato Kosugi , Toshiyuki Fukui
IPC分类号： G06F15/173 , G06F13/362 , G06F13/364 , H04L12/44 , H04B10/20
CPC分类号： H04L12/44 , G06F13/364
摘要： An information processing apparatus transmits data among a plurality of nodes connected to a common transmission line. An arbiter selectively gives use permission, to use the common transmission line for transmitting data, to one of the nodes that requests the use permission on the basis of at least a use request therefor. A data transmission state detector detects the data transmission state on the common transmission line by monitoring for a separate signal on the common transmission line, and notifies the detected state to the arbiter. The arbiter then can use the detected state to give use permission to a requesting node, for example when plural requests are overlappingly received. Advantageously, the separate signal is either an identifier which was added to data and indicates an end of that data, or an identifier that indicates that a current data transmission will be finished after the lapse of a predetermined time.
摘要翻译：信息处理装置在连接到公共传输线路的多个节点之间发送数据。仲裁者根据至少一个使用请求选择性地将使用公共传输线用于发送数据的使用权限提交给请求使用许可的节点之一。数据传输状态检测器通过监视公共传输线上的单独信号来检测公共传输线上的数据传输状态，并将检测到的状态通知给仲裁器。仲裁器然后可以使用检测到的状态来向请求节点授予许可，例如当重复地接收多个请求时。有利地，单独的信号是添加到数据并指示该数据的结束的标识符，或者是在经过预定时间之后指示当前数据传输将被完成的标识符。

4. 发明授权

US6078337A Maintaining consistency of cache memory data by arbitrating use of a connection route by plural nodes 失效
标题翻译：通过仲裁多个节点使用连接路由来保持缓存存储器数据的一致性
公开(公告)号：US6078337A
公开(公告)日：2000-06-20
申请号：US526328
申请日：1995-09-11
申请人： Toshiyuki Fukui , Atsushi Date , Kazumasa Hamaguchi , Masato Kosugi
发明人： Toshiyuki Fukui , Atsushi Date , Kazumasa Hamaguchi , Masato Kosugi
IPC分类号： G06F12/08 , G06F13/16
CPC分类号： G06F12/0815 , G06F12/0813 , G06F2212/2542
摘要： In a system in which a plurality of nodes are connected using a light wavelength multiplexing connection route which can simultaneously connect nodes using light beams of a plurality of different wavelengths, each node has a cache memory for holding data in memories in other nodes. Some or all of the pieces of information required for data transfer in one node or between the nodes are transferred from the node to an arbiter used in use arbitration of the connection route via one of arbitration optical signal routes for respectively connecting the arbiter and the nodes. The arbiter distributes the transferred information to other nodes, and each node updates the contents of its cache memory on the basis of the distributed information.
摘要翻译：在使用可以使用多个不同波长的光束同时连接节点的光波长多路复用连接路径来连接多个节点的系统中，每个节点具有用于将数据保存在其他节点中的存储器中的高速缓冲存储器。在一个节点或节点之间进行数据传输所需的一些或全部信息是通过用于分别连接仲裁器和节点的仲裁光信号路由之一从节点传送到在连接路由的使用仲裁中使用的仲裁器。仲裁器将传送的信息分发到其他节点，每个节点根据分布式信息更新其高速缓冲存储器的内容。

5. 发明授权

US5995751A Information processing apparatus 失效
标题翻译：信息处理装置
公开(公告)号：US5995751A
公开(公告)日：1999-11-30
申请号：US795454
申请日：1997-02-04
申请人： Masato Kosugi , Atsushi Date , Kazumasa Hamaguchi , Toshiyuki Fukui
发明人： Masato Kosugi , Atsushi Date , Kazumasa Hamaguchi , Toshiyuki Fukui
IPC分类号： G06F9/38 , G06F9/312 , G06F9/315 , G06F15/16 , G06F15/78 , G06F15/80 , G06T1/20 , H04N7/24 , H04N19/00 , H04N19/423 , H04N19/436 , H04N19/463 , H04N19/625 , H04N19/70 , H04N19/91 , G06F1/12
CPC分类号： G06F9/30032 , G06F15/8053 , G06F9/30043 , G06F9/3869
摘要： An information processing apparatus in which continuous data of a plurality of series in which the contents of the data of each series are related to each other with respect to time is pipeline processed by a data processing system. The apparatus comprises a plurality of sync generation circuits which correspond to the plurality of series and each of which generate sync signals to instruct timings for the data transfer and data process of each series, and a sync control circuit for controlling generation situations of the sync signals from the plurality of sync generation circuits in accordance with a degree of progress of the data process of each series in the data processing system so that the data of each series can be processed in the data processing system without losing the time-dependent relation.
摘要翻译：一种信息处理装置，其中数据处理系统进行流水线处理，其中每个系列的数据的内容相对于时间彼此相关的多个系列的连续数据。该装置包括对应于多个系列的多个同步产生电路，并且每个同步产生电路产生同步信号以指示每个系列的数据传输和数据处理的定时，以及用于控制同步信号的产生情况的同步控制电路根据数据处理系统中的每个系列的数据处理的进行程度从多个同步产生电路中获取数据，使得可以在数据处理系统中处理每个系列的数据而不失去时间依赖关系。

6. 发明授权

US5923339A Higher-speed parallel processing 失效
标题翻译：更高速的并行处理
公开(公告)号：US5923339A
公开(公告)日：1999-07-13
申请号：US978813
申请日：1997-11-26
申请人： Atsushi Date , Kazumasa Hamaguchi , Masato Kosugi , Toshiyuki Fukui
发明人： Atsushi Date , Kazumasa Hamaguchi , Masato Kosugi , Toshiyuki Fukui
IPC分类号： H04N5/91 , G06F15/16 , G06F15/78 , G06T1/20 , H04N7/24 , H04N19/00 , H04N19/42 , H04N19/423 , H04N19/625 , H04N19/85 , H04N19/91 , G06F15/80
CPC分类号： G06F15/8053
摘要： An information processing apparatus which processes a large amount of data at high speed. The synchronizing signal has a cycle including a transfer period and a processing period. In the transfer period, data is transferred, e.g., from a data input unit to a first memory, and from the first memory to a second memory. In the processing period, the data input unit reads data for one frame of a digital video image, and a data output unit displays an image based on the image data. Processors respectively perform predetermined processing upon data stored in a memory connected to the processor. Thus, within one cycle of the synchronizing signal, processing is completed at respective stages from input to output. Note that the connection between the memories and the processors may be changed for performing the processing at the respective stages without data transfer. In this case, data transfer time can be saved.
摘要翻译：一种高速处理大量数据的信息处理装置。同步信号具有包括传送周期和处理周期的周期。在传送期间，数据例如从数据输入单元传送到第一存储器，并从第一存储器传送到第二存储器。在处理期间，数据输入部读取数字视频图像的一帧的数据，数据输出部根据图像数据显示图像。处理器分别对存储在连接到处理器的存储器中的数据执行预定处理。因此，在同步信号的一个周期内，在从输入到输出的各个阶段完成处理。注意，可以改变存储器和处理器之间的连接，以在不进行数据传送的情况下在各个阶段执行处理。在这种情况下，可以节省数据传输时间。

7. 发明授权

US5602663A Information processing apparatus for multiplex transmission of signal for arbitration and signal for data transfer 失效
标题翻译：信号处理装置，用于多路传输用于仲裁的信号和用于数据传送的信号
公开(公告)号：US5602663A
公开(公告)日：1997-02-11
申请号：US341877
申请日：1994-11-15
申请人： Kazumasa Hamaguchi , Atsushi Date , Masato Kosugi , Toshiyuki Fukui
发明人： Kazumasa Hamaguchi , Atsushi Date , Masato Kosugi , Toshiyuki Fukui
IPC分类号： G06F15/173 , G06F13/00 , H04J1/05 , H04L12/44 , H04Q11/00 , H04J14/02
CPC分类号： H04L12/44 , H04Q11/0062 , H04Q11/0066 , H04Q2011/0015 , H04Q2011/0039 , H04Q2011/0086
摘要： An information processing apparatus has a plurality of computational nodes including a multiplexer and a demultiplexer. A concentrator is connected to the nodes and simultaneously transmits multiplexed signals thereto. An arbiter arbitrates the use of a transmission line for data transfer, with the arbitration and data transfer signals being multiplexed.
摘要翻译：信息处理装置具有包括多路复用器和解复用器的多个计算节点。集中器连接到节点并且同时向其发送多路复用信号。仲裁者对仲裁和数据传输信号进行多路复用来仲裁传输线用于数据传输。

8. 发明授权

US5802295A Information processing method and system therefor 失效
标题翻译：信息处理方法及系统
公开(公告)号：US5802295A
公开(公告)日：1998-09-01
申请号：US525196
申请日：1995-09-08
申请人： Toshiyuki Fukui , Kazumasa Hamaguchi , Masato Kosugi , Tomohiko Shimoyama
发明人： Toshiyuki Fukui , Kazumasa Hamaguchi , Masato Kosugi , Tomohiko Shimoyama
IPC分类号： G06F9/46 , H01J13/00
CPC分类号： G06F9/52
摘要： An information processing method and a system therefor are capable of performing a synchronized operation among CPUs over nodes that cannot monitor each other's internal buses. The system has a plurality of nodes each including one or more CPUs that use monitoring of a common internal bus as a mechanism for synchronizing the CPUs, wherein the plurality of nodes are connected to one another by a connection path that cannot monitor information in a bus in each node. The information processing system includes a transmitter for transmitting information required to perform a synchronized operation in the node or among the nodes through the connection path, and a reflector for reflecting a portion or the overall body of information to the node in accordance with information transmitted by the transmitter so that synchronization of operations of the CPUs over the nodes is realized.
摘要翻译：一种信息处理方法及其系统能够通过不能监视彼此的内部总线的节点在CPU之间执行同步操作。该系统具有多个节点，每个节点包括一个或多个CPU，其使用公共内部总线的监视作为用于使CPU同步的机制，其中多个节点通过不能监视总线中的信息的连接路径彼此连接在每个节点。信息处理系统包括：发送器，用于通过连接路径发送在节点或节点之间执行同步操作所需的信息;以及反射器，用于根据由所述节点发送的信息向所述节点反射信息的一部分或整体，从而实现节点上的CPU的操作的同步。

9. 发明授权

US6021472A Information processing device and control method thereof 失效
标题翻译：信息处理装置及其控制方法
公开(公告)号：US6021472A
公开(公告)日：2000-02-01
申请号：US699943
申请日：1996-08-20
申请人： Kazumasa Hamaguchi , Toshiyuki Fukui , Shuichi Nakamura
发明人： Kazumasa Hamaguchi , Toshiyuki Fukui , Shuichi Nakamura
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0804
摘要： An operation for achieving consistency among copies existing in a plurality of cache memories in a parallel computer system was performed per transaction. If an access issued from a processor to a cache memory is a synchronous access, seeking of a DIRTY block in the cache memory is started. The cache memory issues a bus transaction onto a system bus and performs write back of the DIRTY block in the cache memory relative to a main memory. The write back bus transaction issued from the cache memory in the foregoing fashion is snooped by the other cache memory. With this arrangement, an unnecessary consistency holding operation can be omitted to reduce a delay upon memory accessing in a parallel computer system employing a loose memory consistency model.
摘要翻译：每个交易执行用于实现并行计算机系统中的多个高速缓冲存储器中存在的副本之间的一致性的操作。如果从处理器向高速缓冲存储器发出的访问是同步访问，则开始在高速缓冲存储器中寻找DIRTY块。高速缓存存储器将总线事务发送到系统总线上，并相对于主存储器执行高速缓冲存储器中的DIRTY块的写回。以上述方式从高速缓冲存储器发出的回写总线事务被其他高速缓存存储器窥探。通过这种布置，可以省略不必要的一致性保持操作，以减少采用松散存储器一致性模型的并行计算机系统中的存储器访问时的延迟。

10. 发明授权

US5860110A Conference maintenance method for cache memories in multi-processor system triggered by a predetermined synchronization point and a predetermined condition 失效
标题翻译：由预定同步点和预定条件触发的多处理器系统中的高速缓存存储器的一致性维护方法
公开(公告)号：US5860110A
公开(公告)日：1999-01-12
申请号：US699105
申请日：1996-08-16
申请人： Toshiyuki Fukui , Kazumasa Hamaguchi , Shuichi Nakamura
发明人： Toshiyuki Fukui , Kazumasa Hamaguchi , Shuichi Nakamura
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0813 , G06F12/0804
摘要： When a synchronization point is determined to maintain the coherence of data in a multi-processor system, and data write-back operations from caches to a main memory are simultaneously performed at the determined point, the traffic is concentrated, resulting in poor efficiency. In view of this problem, the write-back operations of cache data are arbitrarily performed when a predetermined condition is satisfied. Alternatively, when the number of copies which are updated in the cache and do not match the corresponding data in the main memory exceeds a predetermined value, cache data are written back. With this control, the write-back operations of copies stored in cache can be prevented from being concentrated at the synchronization point.
摘要翻译：当确定同步点以保持多处理器系统中的数据的一致性，并且在确定的点处同时执行从高速缓存到主存储器的数据回写操作时，流量集中，导致效率差。鉴于这个问题，当满足预定条件时，高速缓存数据的回写操作是任意执行的。或者，当在高速缓存中更新并且与主存储器中的对应数据不匹配的副本数量超过预定值时，高速缓存数据被写回。通过该控制，可以防止存储在高速缓存中的副本的回写操作集中在同步点。

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