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1. 发明申请

US20130069278A1 PATTERN FORMATION DEVICE, METHOD FOR PATTERN FORMATION, AND PROGRAM FOR PATTERN FORMATION 审中-公开
标题翻译：图案形成装置，图案形成方法和图案形成程序
公开(公告)号：US20130069278A1
公开(公告)日：2013-03-21
申请号：US13424427
申请日：2012-03-20
申请人： Sachiko Kobayashi , Kazuhiro Takahata , Yingkang Zhang , Masafumi Asano , Shigeki Nojima
发明人： Sachiko Kobayashi , Kazuhiro Takahata , Yingkang Zhang , Masafumi Asano , Shigeki Nojima
IPC分类号： B29C67/00
CPC分类号： B29C59/026 , B29C59/002 , B29C71/04 , B29K2105/246 , B82Y10/00 , B82Y40/00 , G03F7/0002
摘要： According to one embodiment, a pattern formation device that presses a template that includes a concave and convex part onto a transferring object and that forms a pattern in which a shape of the concave and convex part is transferred is provided. The device includes: a calculation part; an adjustment part; and a transfer. The calculation part calculates, using design information of the pattern, the distribution of force applied to the pattern at a time of releasing the template pressed onto the transferring object from the transferring object. The adjustment part adjusts forming conditions of the pattern in order to uniformly approach the distribution of force calculated by the calculation part. The transfer part transfers the shape of the concave and convex part to the transferring object according to the forming conditions adjusted by the adjustment part.
摘要翻译：根据一个实施例，提供了一种图案形成装置，其将包括凹凸部分的模板按压到转印体上并形成其中转移了凹凸部分的形状的图案。该装置包括：计算部分; 调整部分; 和转移。所述计算部使用所述图案的设计信息，计算从所述转印体上释放压印在所述转印体上的所述模板时施加到所述图案的力的分布。调整部调整图案的成形条件，以均匀地接近由计算部计算出的力的分布。转印部件根据由调节部件调整的成形条件将凹凸部的形状转印到转印体上。

2. 发明授权

US07793252B2 Mask pattern preparation method, semiconductor device manufacturing method and recording medium 失效
标题翻译：掩模图案制备方法，半导体器件制造方法和记录介质
公开(公告)号：US07793252B2
公开(公告)日：2010-09-07
申请号：US12222479
申请日：2008-08-11
申请人： Toshiya Kotani , Shigeki Nojima , Shoji Mimotogi
发明人： Toshiya Kotani , Shigeki Nojima , Shoji Mimotogi
IPC分类号： G06F17/50 , G03F9/00
CPC分类号： G03F7/70433 , G03F7/705
摘要： A lithography simulation method includes: taking in design data of a pattern to be formed on a substrate and mask data to prepare a mask pattern used in forming a latent image of the pattern on the substrate by transmission of an energy ray; obtaining the latent image of the pattern by calculation of an intensity of the energy ray; locally changing, at least in a portion corresponding to a pattern to be interested, a relative position in a direction of the intensity of the energy ray between a latent image curve and a reference intensity line in accordance with a distance between the pattern to be interested and a pattern of a neighboring region, the latent image curve being an intensity distribution curve of the energy ray constituting the latent image, the reference intensity line being defined to specify a position of an edge of the pattern to be interested; and calculating a distance between intersections of a portion of the latent image curve corresponding to the pattern to be interested and the reference intensity line in the changed relative position to define an interested line width of the pattern to be interested.
摘要翻译：光刻模拟方法包括：获取要在基板上形成的图案的设计数据，并且掩模数据，以通过透射能量线来制备用于在基板上形成图案的潜像所使用的掩模图案; 通过计算能量射线的强度来获得图案的潜像; 至少在与感兴趣的图案对应的部分中，根据感兴趣的图案之间的距离，在潜像图像曲线和参考强度线之间的能量射线的强度的方向上的相对位置以及相邻区域的图案，所述潜像曲线是构成所述潜像的能量射线的强度分布曲线，所述基准强度线被定义为指定所述图案的边缘的位置; 以及计算与感兴趣的图案对应的潜在图像曲线的一部分的交点与变化的相对位置中的基准强度线之间的距离，以定义感兴趣的图案的感兴趣的线宽。

3. 发明授权

US07546178B2 Aligner evaluation system, aligner evaluation method, a computer program product, and a method for manufacturing a semiconductor device 有权
标题翻译：对准器评估系统，对准器评估方法，计算机程序产品和半导体器件的制造方法
公开(公告)号：US07546178B2
公开(公告)日：2009-06-09
申请号：US11882620
申请日：2007-08-03
申请人： Takuya Kouno , Shigeki Nojima , Tatsuhiko Higashiki
发明人： Takuya Kouno , Shigeki Nojima , Tatsuhiko Higashiki
IPC分类号： G06F19/00 , G06F17/50
CPC分类号： G03F7/705 , G03F7/70525 , G03F7/70541 , G03F7/70591 , G03F7/70991
摘要： An aligner evaluation system includes (a) an error calculation module configured to calculate error information on mutual optical system errors among a plurality of aligners; (b) a simulation module configured to simulate device patterns to be delineated by each of the aligners based on the error information; and (c) a evaluation module configured to evaluate whether each of the aligners has appropriate performances for implementing an organization of a product development machine group based on the simulated device pattern.
摘要翻译：对准器评估系统包括：（a）误差计算模块，被配置为计算多个对准器之间的相互光学系统误差的误差信息; （b）模拟模块，被配置为基于所述误差信息来模拟由每个对准器描绘的装置模式; 以及（c）评估模块，其被配置为基于所述模拟设备模式来评估每个对准器是否具有用于实现产品开发机器组的组织的适当性能。

4. 发明授权

US07337426B2 Pattern correcting method, mask making method, method of manufacturing semiconductor device, pattern correction system, and computer-readable recording medium having pattern correction program recorded therein 失效
标题翻译：图案校正方法，掩模制作方法，制造半导体器件的方法，图案校正系统以及其中记录有图案校正程序的计算机可读记录介质
公开(公告)号：US07337426B2
公开(公告)日：2008-02-26
申请号：US11115187
申请日：2005-04-27
申请人： Toshiya Kotani , Shigeki Nojima , Kazuhito Kobayashi
发明人： Toshiya Kotani , Shigeki Nojima , Kazuhito Kobayashi
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： There is disclosed a pattern correcting method comprising extracting a correction pattern, at least the one or more correction patterns being included in a first design pattern formed on a substrate, acquiring layout information from the first design pattern, the layout information affecting a finished plane shape of the correction pattern on the substrate, determining contents of correction onto the correction pattern on the basis of the layout information, generating a design pattern-2 corresponding to the layout information so as to be associated with the correction pattern, and correcting the correction pattern in accordance with the contents of correction corresponding to the design pattern-2.
摘要翻译：公开了一种图案校正方法，包括提取校正图案，至少一个或多个校正图案包括在形成在基板上的第一设计图案中，从第一设计图案获取布局信息，影响成品平面形状的布局信息基于所述布局信息确定校正图案的校正内容，生成与所述布局信息对应的设计图案-2以与所述校正图案相关联，以及校正所述校正图案按照与设计模式相对应的修正内容2。

5. 发明授权

US07194704B2 Design layout preparing method 有权
标题翻译：设计布局准备方法
公开(公告)号：US07194704B2
公开(公告)日：2007-03-20
申请号：US11012491
申请日：2004-12-16
申请人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
发明人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5081 , H01L21/0271
摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.
摘要翻译：公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分在维修准则上。

6. 发明申请

US20050251781A1 Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting program 审中-公开
标题翻译：设计模式校正方法，设计模式形成方法，过程接近效应校正方法，半导体器件和设计模式校正程序
公开(公告)号：US20050251781A1
公开(公告)日：2005-11-10
申请号：US11115322
申请日：2005-04-27
申请人： Toshiya Kotani , Shigeki Nojima , Shimon Maeda
发明人： Toshiya Kotani , Shigeki Nojima , Shimon Maeda
IPC分类号： G03C5/00 , G03F1/36 , G03F1/68 , G03F9/00 , G06F17/50 , H01L21/027
CPC分类号： G03F1/36
摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.
摘要翻译：公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度，确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式两个提取的顶点的位置彼此相对。

7. 发明申请

US20050153217A1 Pattern verification method, pattern verification system, mask manufacturing method and semiconductor device manufacturing method 失效
标题翻译：模式验证方法，模式验证系统，掩模制造方法和半导体器件制造方法
公开(公告)号：US20050153217A1
公开(公告)日：2005-07-14
申请号：US11012494
申请日：2004-12-16
申请人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
发明人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G03F9/00 , G06F17/50 , H01L21/027
CPC分类号： G03F7/70441 , G03F1/36
摘要： A pattern verification method comprising preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges, the positional displacement being displacement between first point and the evaluation point, computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.
摘要翻译：一种图案验证方法，包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个工艺参数以计算所转印/形成的图案，定义对于每个过程参数的参考值和可变范围，计算与评估点相对应的每个第一点的位置位移，使用校正掩模图案计算的第一点和通过改变其中的处理参数而获得的参数值的多个组合可变范围或在各个可变范围内，位置偏移是第一点和评估点之间的位移，计算每个评估点的位置偏移的统计，以及根据统计信息输出修改掩模图案的信息。

8. 发明申请

US20120246602A1 METHOD OF PREPARING PATTERN, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：制作图案的方法，制造半导体器件的方法和计算机程序产品
公开(公告)号：US20120246602A1
公开(公告)日：2012-09-27
申请号：US13237663
申请日：2011-09-20
申请人： Sachiko Kobayashi , Satoshi Tanaka , Shigeki Nojima , Kazuhiro Takahata
发明人： Sachiko Kobayashi , Satoshi Tanaka , Shigeki Nojima , Kazuhiro Takahata
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70 , H01L27/0207
摘要： An embodiment provides a method of preparing a pattern. In the pattern preparing method, when mask patterns corresponding to on-substrate patterns are prepared to form the on-substrate patterns corresponding to design patterns, the mask patterns are prepared based on a correlation which needs to be satisfied between the design patterns so that a relation which same the correlation can be satisfied between the mask patterns corresponding to the design patterns.
摘要翻译：实施例提供了一种制备图案的方法。在图案制作方法中，当准备对应于衬底图案的掩模图案以形成与设计图案相对应的衬底上图案时，基于需要在设计图案之间满足的相关性来准备掩模图案，使得在与设计图案对应的掩模图案之间可以满足相关性的关系。

9. 发明授权

US07890908B2 Method for verifying mask pattern data, method for manufacturing mask, mask pattern verification program, and method for manufacturing semiconductor device 有权
标题翻译：用于验证掩模图案数据的方法，用于制造掩模的方法，掩模图案验证程序以及用于制造半导体器件的方法
公开(公告)号：US07890908B2
公开(公告)日：2011-02-15
申请号：US11472441
申请日：2006-06-22
申请人： Shigeki Nojima , Yoko Oikawa , Satoshi Tanaka
发明人： Shigeki Nojima , Yoko Oikawa , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： A method for verifying mask pattern data includes preparing design circuit data on a design circuit which realizes a desired electrical operation. Data on a design circuit pattern having a structure which realizes the design circuit on a semiconductor substrate is prepared. Mask pattern data on a pattern of a mask used in order to produce the design circuit pattern is prepared. A circuit pattern which is to be obtained by processing a film using the pattern of the mask indicated by the mask pattern data is acquired. Circuit data on a circuit realized by at least a first part of the circuit pattern is produced. A circuit mismatch part where the circuit data and a part of the design circuit data which corresponds to the first part of the circuit pattern do not match up is detected.
摘要翻译：一种验证掩模图案数据的方法包括：在设计电路上准备设计电路数据，实现所需的电气操作。制备具有实现半导体衬底上的设计电路的结构的设计电路图案的数据。准备用于产生设计电路图案的掩模图形上的掩模图案数据。获取通过使用由掩模图案数据指示的掩模的图案来处理胶片而获得的电路图案。产生由电路图案的至少第一部分实现的电路上的电路数据。检测与电路图案的第一部分对应的电路数据和设计电路数据的一部分不匹配的电路失配部。

10. 发明授权

US07571417B2 Method and system for correcting a mask pattern design 失效
标题翻译：用于校正掩模图案设计的方法和系统
公开(公告)号：US07571417B2
公开(公告)日：2009-08-04
申请号：US11012494
申请日：2004-12-16
申请人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
发明人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： A pattern verification method includes preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, and computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges. The positional displacement is a displacement between first point and the evaluation point. The method further includes computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.
摘要翻译：模式验证方法包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个过程参数以计算所转移/形成的图案，定义针对每个处理参数的参考值和可变范围，并且计算与评估点相对应的每个第一点的位置偏移，使用校正掩模图案计算的第一点和通过改变处理参数获得的参数值的多个组合在可变范围内或在相应的可变范围内。位置偏移是第一点与评价点之间的位移。该方法还包括计算每个评估点的位置偏移的统计量，并根据统计信息输出修改掩模图案的信息。

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