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1. 发明申请

US20130069278A1 PATTERN FORMATION DEVICE, METHOD FOR PATTERN FORMATION, AND PROGRAM FOR PATTERN FORMATION 审中-公开
标题翻译：图案形成装置，图案形成方法和图案形成程序
公开(公告)号：US20130069278A1
公开(公告)日：2013-03-21
申请号：US13424427
申请日：2012-03-20
申请人： Sachiko Kobayashi , Kazuhiro Takahata , Yingkang Zhang , Masafumi Asano , Shigeki Nojima
发明人： Sachiko Kobayashi , Kazuhiro Takahata , Yingkang Zhang , Masafumi Asano , Shigeki Nojima
IPC分类号： B29C67/00
CPC分类号： B29C59/026 , B29C59/002 , B29C71/04 , B29K2105/246 , B82Y10/00 , B82Y40/00 , G03F7/0002
摘要： According to one embodiment, a pattern formation device that presses a template that includes a concave and convex part onto a transferring object and that forms a pattern in which a shape of the concave and convex part is transferred is provided. The device includes: a calculation part; an adjustment part; and a transfer. The calculation part calculates, using design information of the pattern, the distribution of force applied to the pattern at a time of releasing the template pressed onto the transferring object from the transferring object. The adjustment part adjusts forming conditions of the pattern in order to uniformly approach the distribution of force calculated by the calculation part. The transfer part transfers the shape of the concave and convex part to the transferring object according to the forming conditions adjusted by the adjustment part.
摘要翻译：根据一个实施例，提供了一种图案形成装置，其将包括凹凸部分的模板按压到转印体上并形成其中转移了凹凸部分的形状的图案。该装置包括：计算部分; 调整部分; 和转移。所述计算部使用所述图案的设计信息，计算从所述转印体上释放压印在所述转印体上的所述模板时施加到所述图案的力的分布。调整部调整图案的成形条件，以均匀地接近由计算部计算出的力的分布。转印部件根据由调节部件调整的成形条件将凹凸部的形状转印到转印体上。

2. 发明授权

US08871408B2 Mask pattern creation method, recording medium, and semiconductor device manufacturing method 有权
标题翻译：掩模图案生成方法，记录介质和半导体器件制造方法
公开(公告)号：US08871408B2
公开(公告)日：2014-10-28
申请号：US13604076
申请日：2012-09-05
申请人： Yoko Takekawa , Masafumi Asano , Yingkang Zhang , Kazuhiro Takahata , Tomoko Ojima
发明人： Yoko Takekawa , Masafumi Asano , Yingkang Zhang , Kazuhiro Takahata , Tomoko Ojima
IPC分类号： G03F1/68
CPC分类号： G03F7/0002
摘要： According to one embodiment, a mask pattern creation method includes extracting an area, in which a DSA material is directed self-assembled to form a DSA pattern, from a design pattern area based on a design pattern and information on the DSA material. The method also includes creating a guide pattern that causes the DSA pattern to be formed in the area based on the design pattern, the information on the DSA material, the area, and a design constraint when forming the guide pattern. The method further includes creating a mask pattern of the guide pattern using the guide pattern.
摘要翻译：根据一个实施例，掩模图案创建方法包括基于设计图案和关于DSA材料的信息，从设计图案区域提取其中DSA材料被自组装以形成DSA图案的区域。该方法还包括在形成引导图案时，基于设计图案，关于DSA材料的信息，面积以及设计约束，创建导致DSA图案在该区域中形成的引导图案。该方法还包括使用引导图案创建引导图案的掩模图案。

3. 发明申请

US20120246602A1 METHOD OF PREPARING PATTERN, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：制作图案的方法，制造半导体器件的方法和计算机程序产品
公开(公告)号：US20120246602A1
公开(公告)日：2012-09-27
申请号：US13237663
申请日：2011-09-20
申请人： Sachiko Kobayashi , Satoshi Tanaka , Shigeki Nojima , Kazuhiro Takahata
发明人： Sachiko Kobayashi , Satoshi Tanaka , Shigeki Nojima , Kazuhiro Takahata
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70 , H01L27/0207
摘要： An embodiment provides a method of preparing a pattern. In the pattern preparing method, when mask patterns corresponding to on-substrate patterns are prepared to form the on-substrate patterns corresponding to design patterns, the mask patterns are prepared based on a correlation which needs to be satisfied between the design patterns so that a relation which same the correlation can be satisfied between the mask patterns corresponding to the design patterns.
摘要翻译：实施例提供了一种制备图案的方法。在图案制作方法中，当准备对应于衬底图案的掩模图案以形成与设计图案相对应的衬底上图案时，基于需要在设计图案之间满足的相关性来准备掩模图案，使得在与设计图案对应的掩模图案之间可以满足相关性的关系。

4. 发明申请

US20120198396A1 METHOD OF OPTIMIZING SEMICONDUCTOR DEVICE MANUFACTURING PROCESS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM 审中-公开
标题翻译：优化半导体器件制造工艺的方法，制造半导体器件的方法和非电子计算机可读介质
公开(公告)号：US20120198396A1
公开(公告)日：2012-08-02
申请号：US13237854
申请日：2011-09-20
申请人： Masanari KAJIWARA , Sachiko Kobayashi , Satoshi Tanaka , Kazuhiro Takahata , Shigeki Nojima , Toshiya Kotani , Shimon Maeda
发明人： Masanari KAJIWARA , Sachiko Kobayashi , Satoshi Tanaka , Kazuhiro Takahata , Shigeki Nojima , Toshiya Kotani , Shimon Maeda
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus.
摘要翻译：根据实施例的优化半导体器件制造工艺的方法是优化其中形成基于电路设计的图案的半导体器件制造工艺的方法。根据实施例的半导体器件制造方法的优化方法包括：在基于在第一状态下由第一曝光装置形成的图案与第一状态之间的多个位置处的差异的分布的统计量的计算时，在第二状态下由第二曝光装置形成的图案，基于关于电特性的信息对所述差进行加权计算后的统计量; 并重复进行第二条件的计算，并且选择总和变为最小或等于或小于标准值的条件作为第二曝光装置的优化条件。

5. 发明申请

US20110224934A1 EVALUATING APPARATUS, EVALUATING METHOD, AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：评估设备，评估方法和计算机程序产品
公开(公告)号：US20110224934A1
公开(公告)日：2011-09-15
申请号：US12882998
申请日：2010-09-15
申请人： Seiro Miyoshi , Hideaki Abe , Kazuhiro Takahata , Masafumi Asano , Shoji Mimotogi , Tomoko Ojima , Masanari Kajiwara
发明人： Seiro Miyoshi , Hideaki Abe , Kazuhiro Takahata , Masafumi Asano , Shoji Mimotogi , Tomoko Ojima , Masanari Kajiwara
IPC分类号： G06F19/00
CPC分类号： G03F7/70625 , G03F7/70525 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, an evaluating apparatus includes a resist-pattern-data acquiring unit and an evaluating unit. The resist-pattern-data acquiring unit acquires resist pattern data having a plurality of feature values including at least two among a hole diameter measured concerning a pattern for hole formation in the resist pattern, an aspect ratio of the hole diameter, and a difference of hole diameters at a plurality of signal thresholds. The evaluating unit calculates an evaluation value using an evaluation function for evaluating whether a hole pattern formed on a processing target by using the pattern for hole formation is unopened and the resist pattern data and evaluates presence or absence of a risk that the hole pattern is unopened.
摘要翻译：根据一个实施例，评估装置包括抗蚀剂图案数据获取单元和评估单元。抗蚀剂图案数据获取单元获取具有多个特征值的抗蚀剂图案数据，所述多个特征值包括测量的关于抗蚀剂图案中的孔形成图案的孔直径，孔直径的纵横比和孔径在多个信号阈值。评价单元使用评价函数来计算评价值，该评价函数用于评估是否未打开通过使用用于形成孔的图案而形成在处理对象上的孔图案，并且抵抗图案数据并评估是否存在未打开孔图案的风险。

6. 发明授权

US08158527B2 Semiconductor device fabrication method using multiple resist patterns 有权
标题翻译：使用多个抗蚀剂图案的半导体器件制造方法
公开(公告)号：US08158527B2
公开(公告)日：2012-04-17
申请号：US12724115
申请日：2010-03-15
申请人： Koji Hashimoto , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
发明人： Koji Hashimoto , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
IPC分类号： H01L21/302
CPC分类号： G03F7/0035 , H01L21/0338 , H01L21/28123 , H01L21/32139 , H01L21/823456 , H01L21/823475 , H01L27/10873 , H01L27/10894 , H01L27/10897
摘要： A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
摘要翻译：在工作薄膜（3）上的硬掩模材料膜（4）上的曝光分辨率的限制的尺寸形成抗蚀剂图案（5）。使用抗蚀剂图案（5）作为掩模来处理材料膜（4）。由此形成硬掩模图案（6）。由此，形成具有开口（7a）的非选择区域（6b）上的抗蚀剂图案（7），掩模图案中的选择区域（6a）穿过该开口7a露出。通过进行选择蚀刻，只有通过开口（7a）露出的掩模图案（6a）变薄，通过使用掩模图案（6）蚀刻工作膜（3）。由此形成工作胶片图案（8），其包括具有限制曝光分辨率的尺寸宽度的宽图案部分（8a）和尺寸不大于限制的尺寸的纤薄图案部分（8a）曝光分辨率。

7. 发明授权

US07824996B2 Semiconductor device fabrication method and semiconductor device 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US07824996B2
公开(公告)日：2010-11-02
申请号：US12724019
申请日：2010-03-15
申请人： Koji Hashimoto , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
发明人： Koji Hashimoto , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
IPC分类号： H01L21/302
CPC分类号： G03F7/0035 , H01L21/0338 , H01L21/28123 , H01L21/32139 , H01L21/823456 , H01L21/823475 , H01L27/10873 , H01L27/10894 , H01L27/10897
摘要： A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
摘要翻译：在工作薄膜（3）上的硬掩模材料膜（4）上的曝光分辨率的限制的尺寸形成抗蚀剂图案（5）。使用抗蚀剂图案（5）作为掩模来处理材料膜（4）。由此形成硬掩模图案（6）。由此，形成具有开口（7a）的非选择区域（6b）上的抗蚀剂图案（7），掩模图案中的选择区域（6a）穿过该开口7a露出。通过进行选择蚀刻，只有通过开口（7a）露出的掩模图案（6a）变薄，通过使用掩模图案（6）蚀刻工作膜（3）。由此形成工作胶片图案（8），其包括具有限制曝光分辨率的尺寸宽度的宽图案部分（8a）和尺寸不大于限制的尺寸的纤薄图案部分（8a）曝光分辨率。

8. 发明申请

US20090119635A1 MASK PATTERN CORRECTION METHOD FOR MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路器件制造掩模图形校正方法
公开(公告)号：US20090119635A1
公开(公告)日：2009-05-07
申请号：US11949588
申请日：2007-12-03
申请人： Kazuhiro Takahata
发明人： Kazuhiro Takahata
IPC分类号： G06F17/50
CPC分类号： G03F7/70625 , G03F1/36 , G03F1/68
摘要： Mask data is generated from a design layout by executing a mask data process including optical proximity correction. A pattern is formed on the major surface of a test semiconductor substrate by using a mask prepared from the mask data. The dimensional difference between the design layout and the pattern is measured. The design layout is corrected, at a portion with the dimensional difference of the design layout, by the magnitude of the dimensional difference in a direction in which the dimensions of the pattern equal those of the design layout, thereby generating a corrected design layout. Corrected mask data is generated from the corrected design layout by executing the mask data process including the optical proximity correction. A pattern is formed on the major surface of a semiconductor substrate by using a corrected mask prepared from the corrected mask data.
摘要翻译：通过执行包括光学邻近校正的掩模数据处理，从设计布局生成掩模数据。通过使用由掩模数据制备的掩模，在测试半导体衬底的主表面上形成图案。测量设计布局与图案之间的尺寸差异。在设计布局的尺寸差异的部分，通过在图案的尺寸等于设计布局的尺寸的方向上的尺寸差的大小来校正设计布局，从而生成校正的设计布局。通过执行包括光学邻近校正的掩模数据处理，从校正的设计布局生成校正的掩模数据。通过使用从校正的掩模数据制备的校正掩模，在半导体衬底的主表面上形成图案。

9. 发明申请

US20100196809A1 SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US20100196809A1
公开(公告)日：2010-08-05
申请号：US12724019
申请日：2010-03-15
申请人： Koji HASHIMOTO , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
发明人： Koji HASHIMOTO , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
IPC分类号： G03F7/20
CPC分类号： G03F7/0035 , H01L21/0338 , H01L21/28123 , H01L21/32139 , H01L21/823456 , H01L21/823475 , H01L27/10873 , H01L27/10894 , H01L27/10897
摘要： A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
摘要翻译：在工作薄膜（3）上的硬掩模材料膜（4）上的曝光分辨率的限制的尺寸形成抗蚀剂图案（5）。使用抗蚀剂图案（5）作为掩模来处理材料膜（4）。由此形成硬掩模图案（6）。由此，形成具有开口（7a）的非选择区域（6b）上的抗蚀剂图案（7），掩模图案中的选择区域（6a）穿过该开口7a露出。通过进行选择蚀刻，只有通过开口（7a）露出的掩模图案（6a）变薄，通过使用掩模图案（6）蚀刻工作膜（3）。由此形成工作胶片图案（8），其包括具有限制曝光分辨率的尺寸宽度的宽图案部分（8a）和尺寸不大于限制的尺寸的纤薄图案部分（8a）曝光分辨率。

10. 发明申请

US20070105391A1 Semiconductor device fabrication method and semiconductor device 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US20070105391A1
公开(公告)日：2007-05-10
申请号：US11643907
申请日：2006-12-22
申请人： Koji Hashimoto , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
发明人： Koji Hashimoto , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
IPC分类号： H01L21/302 , H01L21/3205 , H01L21/8234
CPC分类号： G03F7/0035 , H01L21/0338 , H01L21/28123 , H01L21/32139 , H01L21/823456 , H01L21/823475 , H01L27/10873 , H01L27/10894 , H01L27/10897
摘要： A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section. (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
摘要翻译：在工作薄膜（3）上的硬掩模材料膜（4）上的曝光分辨率的限制的尺寸形成抗蚀剂图案（5）。使用抗蚀剂图案（5）作为掩模来处理材料膜（4）。由此形成硬掩模图案（6）。由此，在非选择区域（6b）上形成具有开口（7a）的抗蚀剂图案（7），掩模图案中的选择区域（6a）通过该开口暴露。仅通过开口（7a）暴露的掩模图案（6a）通过进行选择蚀刻而变薄，通过使用掩模图案（6）蚀刻工作膜（3）。由此形成工作膜图案（8），其包括宽图案部分。（8a）限定曝光分辨率的尺寸宽度和不大于曝光分辨率限制的尺寸的纤薄图案部分（8a）。

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