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1. 发明授权

US5890189A Memory management and protection system for virtual memory in computer system 失效
标题翻译：计算机系统虚拟内存的内存管理和保护系统
公开(公告)号：US5890189A
公开(公告)日：1999-03-30
申请号：US753944
申请日：1996-12-03
申请人： Hiroshi Nozue , Mitsuo Saito , Kenichi Maeda , Shigehiro Asano , Toshio Okamoto , Shin Sungho , Hideo Segawa
发明人： Hiroshi Nozue , Mitsuo Saito , Kenichi Maeda , Shigehiro Asano , Toshio Okamoto , Shin Sungho , Hideo Segawa
IPC分类号： G06F12/10 , G06F12/14 , G06F12/00
CPC分类号： G06F12/1458 , G06F12/109 , G06F12/1483 , G06F12/1491 , G06F2212/656
摘要： A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched. Also, it is preferable to allocate a plurality of programs within a limit of available memory protection capacity to an identical logical address space, without any overlap between adjacently allocated address regions.
摘要翻译：一种用于实现高速执行的存储器管理和保护系统，以及用于共享相同逻辑地址空间的多个程序的适当且灵活的存储器访问控制。在系统中，根据标识逻辑地址空间中的段的段标识符，允许存储器访问，以及每个区段中的区域的存储器保护信息，包括目标权限，以指示从存储器访问的指定的权限区域，以及用于指示由权限许可允许的存储器访问的类型的执行许可。或者，可以通过使用附加到每个地址表条目的访问控制列表来允许存储器访问，每个地址表条目存储多个程序号，标识被允许访问存储在每个地址表条目中的逻辑地址的程序，将搜索与当前节目号匹配的那个。此外，优选地，在可用存储器保护容量的限制内将多个程序分配给相同的逻辑地址空间，而不会在相邻分配的地址区域之间发生任何重叠。

2. 发明授权

US06820187B2 Multiprocessor system and control method thereof 失效
标题翻译：多处理器系统及其控制方法
公开(公告)号：US06820187B2
公开(公告)日：2004-11-16
申请号：US09989028
申请日：2001-11-21
申请人： Shigehiro Asano , Mitsuo Saito
发明人： Shigehiro Asano , Mitsuo Saito
IPC分类号： G06F15163
CPC分类号： G06F13/28
摘要： A multiprocessor system including a master processor, a plurality of processor elements, each of which is provided with a local memory, the processor elements being controlled in accordance with commands from the foregoing master processor, and a global memory shared by the plurality of processor elements is disclosed. The processor elements are provided with a command pooling buffer capable of accumulating a plurality of commands, respectively. DMA controllers are also provided with a command pooling buffer capable of accumulating a plurality of commands, respectively. The master processor persistently issues a plurality of commands to the DMA controller and each processor element. A counter array manages the number of the issued commands which have received no response. When the responses are returned with respect to all issued commands, the counter array notifies the master processor of this.
摘要翻译：一种多处理器系统，包括主处理器，多个处理器元件，每个处理器元件具有本地存储器，处理器元件根据来自前述主处理器的命令进行控制，以及由多个处理器元件共享的全局存储器被披露。处理器元件设置有分别能够累积多个命令的命令池缓冲器。 DMA控制器还具有能分别累积多个命令的命令池缓冲器。主处理器持续向DMA控制器和每个处理器元件发出多个命令。计数器阵列管理没有响应的已发出命令的数量。当相对于所有发出的命令返回响应时，计数器阵列通知主处理器。

3. 发明授权

US5627987A Memory management and protection system for virtual memory in computer system 失效
标题翻译：计算机系统虚拟内存的内存管理和保护系统
公开(公告)号：US5627987A
公开(公告)日：1997-05-06
申请号：US21098
申请日：1993-02-23
申请人： Hiroshi Nozue , Mitsuo Saito , Kenichi Maeda , Shigehiro Asano , Toshio Okamoto , Shin Sungho , Hideo Segawa
发明人： Hiroshi Nozue , Mitsuo Saito , Kenichi Maeda , Shigehiro Asano , Toshio Okamoto , Shin Sungho , Hideo Segawa
IPC分类号： G06F12/10 , G06F12/14 , G06F12/00
CPC分类号： G06F12/1458 , G06F12/109 , G06F12/1483 , G06F12/1491 , G06F2212/656
摘要： A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched. Also, it is preferable to allocate a plurality of programs within a limit of available memory protection capacity to an identical logical address space, without any overlap between adjacently allocated address regions.
摘要翻译：一种用于实现高速执行的存储器管理和保护系统，以及用于共享相同逻辑地址空间的多个程序的适当且灵活的存储器访问控制。在系统中，根据标识逻辑地址空间中的段的段标识符，允许存储器访问，以及每个区段中的区域的存储器保护信息，包括目标权限，以指示从存储器访问的指定的权限区域，以及用于指示由权限许可允许的存储器访问的类型的执行许可。或者，可以通过使用附加到每个地址表条目的访问控制列表来允许存储器访问，每个地址表条目存储多个程序号，标识被允许访问存储在每个地址表条目中的逻辑地址的程序，将搜索与当前节目号匹配的那个。此外，优选地，在可用存储器保护容量的限制内将多个程序分配给相同的逻辑地址空间，而不会在相邻分配的地址区域之间发生任何重叠。

4. 发明授权

US07654360B2 Motor-driven steering apparatus 有权
标题翻译：电动转向装置
公开(公告)号：US07654360B2
公开(公告)日：2010-02-02
申请号：US11520875
申请日：2006-09-14
申请人： Mitsuo Saito , Isamu Arai
发明人： Mitsuo Saito , Isamu Arai
IPC分类号： B62D15/02
CPC分类号： B62D5/04 , B62D1/16 , B62D1/20 , B62D5/0409 , B62K5/01 , B62K5/08
摘要： In a motor-driven steering apparatus structured such that a motor-driven steering assist unit is interposed between a steering shaft in a handle side and a wheel side steering member, and an input shaft connected to the steering shaft of the motor-driven steering assist unit and an output shaft connected to the wheel side steering member are coupled by a torsion bar and arranged on the same center axis, reference angle position marks are applied to portions existing at the same angle position around the same center axis of the input shaft and the output shaft, in a neutral steering state in which a steering force is not applied to the input shaft of the motor-driven steering assist unit.
摘要翻译：在电机驱动的转向装置中，电机驱动的转向辅助单元被插入在手柄侧的转向轴与车轮侧的转向构件之间，以及连接到电动助力转向辅助的转向轴的输入轴连接到车轮侧转向构件的单元和输出轴通过扭杆联接并且布置在相同的中心轴上，参考角位置标记被施加到围绕输入轴的相同中心轴线的相同角度位置处存在的部分，所述输出轴处于不向所述电动助力转向辅助单元的输入轴施加转向力的中立转向状态。

5. 发明授权

US07540511B2 Support structure of motor-driven steering assist apparatus 有权
标题翻译：电动转向辅助装置的支撑结构
公开(公告)号：US07540511B2
公开(公告)日：2009-06-02
申请号：US11900960
申请日：2007-09-14
申请人： Mitsuo Saito , Koichi Hata , Hideo Yanai
发明人： Mitsuo Saito , Koichi Hata , Hideo Yanai
IPC分类号： B62D7/22
CPC分类号： B62D5/0403 , B62D1/16 , B62D5/0409
摘要： In a support structure of a motor-driven steering assist apparatus interposed between an upper steering shaft in a steering wheel side and a lower steering shaft in a tire wheel side, a steering angle regulating means for limiting a maximum steering angle of the upper steering shaft is provided between the upper steering shaft and a vehicle body side and a steering angle regulating means for limiting a maximum steering angle of the lower steering shaft is provided between the lower steering shaft and the vehicle body side.
摘要翻译：在设置在方向盘一侧的上转向轴和轮胎车轮侧的下转向轴之间的电动助力转向辅助装置的支撑结构中，限制上转向轴的最大转向角的转向角调节装置设置在上转向轴和车体侧之间，并且在下转向轴和车体侧之间设置用于限制下转向轴的最大转向角的转向角调节装置。

6. 发明授权

US5561774A Parallel processing type processor system with trap and stall control functions 失效
标题翻译：并行处理型处理器系统具有陷波和失速控制功能
公开(公告)号：US5561774A
公开(公告)日：1996-10-01
申请号：US291582
申请日：1994-08-16
申请人： Takeshi Aikawa , Mitsuo Saito , Kenji Minagawa , Kenji Takeda
发明人： Takeshi Aikawa , Mitsuo Saito , Kenji Minagawa , Kenji Takeda
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3863 , G06F9/3885
摘要： A parallel processing type processor system with trap and stall control functions capable of operating without increasing the cycle time, such that the lowering of the clock frequency in the system can be prevented. In the system, the processor units are controlled such that when an exception is caused in an execution of at least one of the instructions supplied to the processor units concurrently, the processings of all of the instructions supplied to the processor units concurrently are aborted. In addition, the processings of the instructions supplied to the processor units concurrently are stalled when it is not possible to deny a possibility for an occurrence of an exception in the execution of the instructions supplied to the processor units concurrently.
摘要翻译：一种具有陷波和失速控制功能的并行处理型处理器系统，其能够在不增加周期时间的情况下进行操作，从而可以防止系统中的时钟频率的降低。在该系统中，处理器单元被控制，使得当在执行提供给处理器单元的至少一个指令的同时执行异常时，同时提供给处理器单元的所有指令的处理被中止。此外，当不可能在执行提供给处理器单元的指令的同时拒绝发生异常的可能性时，同时提供给处理器单元的指令的处理被停止。

7. 发明授权

US5414822A Method and apparatus for branch prediction using branch prediction table with improved branch prediction effectiveness 失效
标题翻译：使用具有改进的分支预测有效性的分支预测表进行分支预测的方法和装置
公开(公告)号：US5414822A
公开(公告)日：1995-05-09
申请号：US863181
申请日：1992-04-03
申请人： Mitsuo Saito , Takeshi Aikawa , Junji Mori
发明人： Mitsuo Saito , Takeshi Aikawa , Junji Mori
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/3806 , G06F9/3844
摘要： The branch prediction using a branch prediction table formed by an associative memory which is applicable to a super scalar processor without causing confusion in the branch prediction. The branch prediction uses a branch prediction table for registering entries, each entry including a branching address, a branch target address, and an instruction position indicating a position of the predicted branch instruction in group of instructions to be executed concurrently, or an entry address indicating a position of each entry in the associative memory of the table. A correctness of the predicted branch instruction is checked by using actual branch target address and/or actual instruction position of actual branch instruction encountered in the actual execution of presently fetched instructions. When the predicted branch instruction is incorrect, instructions fetched at a next processing timing are invalidated and the entry in the table is rewritten.
摘要翻译：该分支预测使用由适用于超标量处理器的关联存储器形成的分支预测表，而不会导致分支预测中的混淆。分支预测使用用于登记条目的分支预测表，每个条目包括分支地址，分支目标地址和指示同时执行的指令组中的预测分支指令的位置的指示位置，或指示每个条目在表的关联记忆中的位置。通过使用实际分支目标地址和/或在当前取得的指令的实际执行中遇到的实际分支指令的实际指令位置来检查预测分支指令的正确性。当预测分支指令不正确时，在下一个处理定时取出的指令无效，表中的条目被重写。

8. 发明授权

US5163127A Three dimensional graphic processing apparatus 失效
标题翻译：三维图形处理装置
公开(公告)号：US5163127A
公开(公告)日：1992-11-10
申请号：US687772
申请日：1991-04-19
申请人： Nobuyuki Ikumi , Mitsuo Saito , Takeshi Aikawa , Masahide Ohhashi
发明人： Nobuyuki Ikumi , Mitsuo Saito , Takeshi Aikawa , Masahide Ohhashi
IPC分类号： G06T15/40 , G06T15/80
CPC分类号： G06T15/87
摘要： A three-dimensional graphic processing apparatus includes n arithmetic ICs (Integrated Circuits) for performing linear interpolation calculations for each scan line of a triangle polygon to obtain intensity values and depth coordinate values of pixels, and two types of n memories for storing the calculation results. The n arithmetic ICs parallelly execute linear interpolation calculations of n different pixels successive on a single scan line of a single triangle polygon in one processing cycle. Each arithmetic IC calculates for each of every n pixels in one processing cycle, and a corresponding one of the memories stores the calculation result.
摘要翻译：三维图形处理装置包括用于对三角形多边形的每条扫描线进行线性插值计算的n个运算IC（集成电路），以获得像素的强度值和深度坐标值，以及用于存储计算结果的两种类型的n个存储器。在一个处理周期中，n个运算IC并行地执行在单个三角形多边形的单个扫描线上连续的n个不同像素的线性插值计算。每个算术IC在一个处理周期中为每n个像素计算每个运算IC，并且相应的一个存储器存储计算结果。

9. 发明授权

US5067593A Braking device for elevator winding machine and elevator using the braking device 失效
标题翻译：用于电梯绕线机的制动装置和使用制动装置的电梯
公开(公告)号：US5067593A
公开(公告)日：1991-11-26
申请号：US438014
申请日：1989-11-20
申请人： Masakatsu Tanaka , Masanobu Itoh , Noboru Arabori , Toshihiko Nara , Tastuhiko Takahashi , Katutaro Masuda , Mitsuo Saito
发明人： Masakatsu Tanaka , Masanobu Itoh , Noboru Arabori , Toshihiko Nara , Tastuhiko Takahashi , Katutaro Masuda , Mitsuo Saito
IPC分类号： B66B11/08 , B66B1/28 , B66B5/04 , B66D5/14 , B66D5/30 , F16D55/00 , F16D55/28 , F16D59/02 , F16D65/14 , F16D65/18 , F16D69/04
CPC分类号： F16D55/28 , B66B1/28 , B66B5/04 , B66D5/14 , B66D5/30 , F16D59/02 , F16D2055/0058 , F16D2065/383 , F16D2121/22 , Y10T477/393
摘要： A braking device for an elevator winding machine generates a braking force by contacting a rotary body driven by a rotary shaft of the winding machine with a brake section supported through the intermediary of an elastic body. The elastic body has a nonlinear elastic characteristic so that a starting shock to the passengers in the elevator car is prevented and the braking torque detecting accuracy is improved.
摘要翻译：用于电梯绕线机的制动装置通过使由绕线机的旋转轴驱动的旋转体与通过弹性体的中间支撑的制动部分接触而产生制动力。该弹性体具有非线性的弹性特性，能够防止对电梯轿厢的乘客的起动冲击，提高制动转矩检测精度。

10. 发明授权

US4992977A Cache memory device constituting a memory device used in a computer 失效
标题翻译：构成计算机中使用的存储装置的高速缓存存储装置
公开(公告)号：US4992977A
公开(公告)日：1991-02-12
申请号：US173296
申请日：1988-03-25
申请人： Tsukasa Matoba , Takeshi Aikawa , Ken-ichi Maeda , Mitsuo Saito , Mitsuyoshi Okamura
发明人： Tsukasa Matoba , Takeshi Aikawa , Ken-ichi Maeda , Mitsuo Saito , Mitsuyoshi Okamura
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3812 , G06F12/0804 , G06F12/0848
摘要： A cache memory device comprises a data cache memory, an instruction cache memory, an instruction code area change detector, and an instruction code change processor. The instruction code area change detector decides whether writing access to the data cache memory by the processor is to a data area or to an instruction area of a main memory. The instruction code change processor passes the data cache memory to perform direct writing into the main memory when the writing access is to the instruction area, and, when data for a processor address is cached in a tag section of the instruction cache memory, invalidates the effective flag of the tag section.
摘要翻译：高速缓冲存储器装置包括数据高速缓存存储器，指令高速缓存存储器，指令代码区域改变检测器和指令代码改变处理器。指令代码区域改变检测器决定处理器对数据高速缓冲存储器的写入写入是到数据区还是主存储器的指令区。当写入访问指令区时，指令代码变更处理器通过数据高速缓冲存储器来执行直接写入主存储器，并且当处理器地址的数据被缓存在指令高速缓存存储器的标签部分中时，使标签部分的有效标志。

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