专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140082263A1 MEMORY SYSTEM 审中-公开
标题翻译：记忆系统
公开(公告)号：US20140082263A1
公开(公告)日：2014-03-20
申请号：US14004788
申请日：2011-09-20
申请人： Shigeaki Iwasa , Kohei Oikawa
发明人： Shigeaki Iwasa , Kohei Oikawa
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/0659 , G06F3/0679
摘要： According to one embodiment, a memory system includes a plurality of nonvolatile memories, an address converter, a plurality of channel controllers, and a controller. The plurality of nonvolatile memories is connected to respective channels. The address converter converts a logical address of a read request into a physical address of the nonvolatile memories. Each of the channel controllers is provided to each of the channels. Each of the channel controllers has a plurality of queues, each queues stores at least two read request. The controller selects a queue which stores no read request, and transfers the read request to the selected queue.
摘要翻译：根据一个实施例，存储器系统包括多个非易失性存储器，地址转换器，多个通道控制器和控制器。多个非易失性存储器连接到相应的通道。地址转换器将读请求的逻辑地址转换为非易失性存储器的物理地址。每个通道控制器被提供给每个通道。每个信道控制器具有多个队列，每个队列存储至少两个读请求。控制器选择不存储读取请求的队列，并将读取的请求传送到所选择的队列。

2. 发明授权

US07610504B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07610504B2
公开(公告)日：2009-10-27
申请号：US11779084
申请日：2007-07-17
申请人： Kohei Oikawa
发明人： Kohei Oikawa
IPC分类号： G06F1/12 , G06F1/00
CPC分类号： G06F1/10 , G06F1/12 , G06F1/26
摘要： A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the first clock distribution network, and a second phase synchronizer which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the second clock distribution network. The semiconductor integrated circuit has a mode for changing a value of the second power supply voltage to a value which is different from a value of the first power supply voltage.
摘要翻译：一种半导体集成电路，包括提供有第一电源电压的第一电源区域，并具有第一时钟分配网络，提供有第二电源电压的第二电源区域，以及具有第二时钟分配网络的第一阶段同步器，其提供通过使得用于控制与第一时钟分配网络的第一点处的时钟信号的相位一致的数据输入/输出的参考时钟信号的相位而获得的第一输出信号到第一时钟信号的第二点时钟分配网络和第二相位同步器，其提供通过使参考时钟信号的相位与第二时钟分配网络的第一点处的时钟信号的相位一致而获得的第二输出信号到第二时钟分配网络的第二点第二时钟分配网络。半导体集成电路具有将第二电源电压的值改变为与第一电源电压的值不同的值的模式。

3. 发明授权

US07154766B2 Ferroelectric memory 有权
公开(公告)号：US07154766B2
公开(公告)日：2006-12-26
申请号：US10934358
申请日：2004-09-07
申请人： Kohei Oikawa , Daisaburo Takashima
发明人： Kohei Oikawa , Daisaburo Takashima
IPC分类号： G11C11/22 , G11C11/42 , G11C7/00 , G11C7/02 , G11C8/00 , G11C8/18
CPC分类号： G11C11/22
摘要： An aspect of the present invention provides a ferroelectric memory comprising a cell block having a plurality of unit cells connected in series, one end of the cell block being connected to a plate line and the other end of the cell block being connected to a bit line through a block selecting transistor, a sense amplifier connected to the bit line, and a block selector decoder which controls ON/OFF of the block selecting transistor. The timing for operating the sense amplifier and block selector decoder is changed corresponding to a position of a selected unit cell objective for data read of the plurality of unit cells.

4. 发明授权

US07016216B2 Ferroelectric memory device having ferroelectric capacitor and method of reading out data therefrom 失效
标题翻译：具有铁电电容器的铁电存储器件和从其读出数据的方法
公开(公告)号：US07016216B2
公开(公告)日：2006-03-21
申请号：US10680394
申请日：2003-10-08
申请人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
发明人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes memory cells, a memory cell block, a sense amplifier, a precharge circuit, a bit line drive circuit, and a plate line drive circuit. Each of the memory cells has a cell transistor and a ferroelectric capacitor in between a source and drain of the cell transistor. The memory cell block includes the memory cells that are series connected between a bit line via a block select transistor and a plate line. The sense amplifier amplifies data read out from the memory cell, and generates one of a first potential and a second potential higher than the first potential in accordance with the read-out data. The precharge circuit precharges the bit line at a third potential that is higher than the first potential and lower than the second potential. The bit line drive circuit sets the bit line at a fourth potential.
摘要翻译：铁电存储器件包括存储单元，存储单元块，读出放大器，预充电电路，位线驱动电路和板线驱动电路。每个存储单元在单元晶体管的源极和漏极之间具有单元晶体管和铁电电容器。存储单元块包括串联连接在经由块选择晶体管的位线和板线之间的存储单元。读出放大器放大从存储单元读出的数据，根据读出的数据产生高于第一电位的第一电位和第二电位中的一个。预充电电路在比第一电位高且低于第二电位的第三电位预充电位线。位线驱动电路将位线设置为第四个电位。

5. 发明申请

US20060018144A1 Ferroelectric memory 有权
标题翻译：铁电存储器
公开(公告)号：US20060018144A1
公开(公告)日：2006-01-26
申请号：US10934358
申请日：2004-09-07
申请人： Kohei Oikawa , Daisaburo Takashima
发明人： Kohei Oikawa , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： An aspect of the present invention provides a ferroelectric memory comprising a cell block having a plurality of unit cells connected in series, one end of the cell block being connected to a plate line and the other end of the cell block being connected to a bit line through a block selecting transistor, a sense amplifier connected to the bit line, and a block selector decoder which controls ON/OFF of the block selecting transistor. The timing for operating the sense amplifier and block selector decoder is changed corresponding to a position of a selected unit cell objective for data read of the plurality of unit cells.
摘要翻译：本发明的一个方面提供一种铁电存储器，其包括具有多个串联连接的单位单元的单元块，所述单元块的一端连接到板线，并且所述单元块的另一端连接到位线通过块选择晶体管，连接到位线的读出放大器和控制块选择晶体管的导通/截止的块选择器解码器。用于操作读出放大器和块选择器解码器的定时对应于用于多个单位单元的数据读取的所选择的单位单元目标的位置而改变。

6. 发明授权

US08977890B2 Memory system and control method 有权
标题翻译：内存系统和控制方法
公开(公告)号：US08977890B2
公开(公告)日：2015-03-10
申请号：US13722149
申请日：2012-12-20
申请人： Kohei Oikawa
发明人： Kohei Oikawa
IPC分类号： G06F11/00 , G06F12/02 , G06F11/16 , G06F11/10 , G06F1/32
CPC分类号： G06F12/0246 , G06F1/3275 , G06F11/1048 , G06F11/167 , G06F2212/1028 , G06F2212/7207 , Y02D10/13 , Y02D10/14
摘要： According to one embodiment, a memory system includes a first memory, a second memory, and a control unit. The first memory includes a volatile first register retaining a first operation parameter. The control unit performs a first operation of retaining the first operation parameter in the second memory. Then, the control unit turns OFF the first memory while retaining the first operation parameter in the second memory when an operation mode is switched from a first mode to a power saving second mode. Then, the control unit performs a second operation of turning on the first memory, and transferring the first operation parameter retained in the second memory to the first register when the operation mode is switched from the second mode to the first mode.
摘要翻译：根据一个实施例，存储器系统包括第一存储器，第二存储器和控制单元。第一存储器包括保持第一操作参数的易失性第一寄存器。控制单元执行将第一操作参数保持在第二存储器中的第一操作。然后，当操作模式从第一模式切换到省电第二模式时，控制单元将第一存储器保持第二操作参数保持在第二存储器中。然后，当操作模式从第二模式切换到第一模式时，控制单元执行打开第一存储器的第二操作，以及将保存在第二存储器中的第一操作参数传送到第一寄存器。

7. 发明授权

US07650521B2 Semiconductor integrated circuit having a first power supply region and a second power supply region in which power supply voltage changes 失效
标题翻译：具有电源电压变化的第一电源区域和第二电源区域的半导体集成电路
公开(公告)号：US07650521B2
公开(公告)日：2010-01-19
申请号：US11779071
申请日：2007-07-17
申请人： Kohei Oikawa
发明人： Kohei Oikawa
IPC分类号： G06F1/00 , G06F1/12
CPC分类号： G06F1/10 , G06F1/12 , G06F1/26
摘要： A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the second clock distribution network, and a second phase synchronizer which provides a second output signal obtained by making the phase of the clock signal at a third point of the first clock distribution network coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the first clock distribution network. The semiconductor integrated circuit has a mode for changing a value of the second power supply voltage to a value which is different from a value of the first power supply voltage.
摘要翻译：一种半导体集成电路，包括提供有第一电源电压的第一电源区域，并具有第一时钟分配网络，提供有第二电源电压的第二电源区域，以及具有第二时钟分配网络的第一阶段同步器，其提供通过使第一时钟分配网络的第一点处的与时钟信号的相位一致的数据输入/输出的参考时钟信号的相位获得的第一输出信号到第二时钟信号的第二点时钟分配网络和第二相位同步器，其提供通过使第一时钟分配网络的第三点处的时钟信号的相位与第二时钟的第一点处的时钟信号的相位一致而获得的第二输出信号分销网络，到第一个时钟分配网络的第二点。半导体集成电路具有将第二电源电压的值改变为与第一电源电压的值不同的值的模式。

8. 发明申请

US20080016377A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20080016377A1
公开(公告)日：2008-01-17
申请号：US11779071
申请日：2007-07-17
申请人： Kohei Oikawa
发明人： Kohei Oikawa
IPC分类号： G06F1/26
CPC分类号： G06F1/10 , G06F1/12 , G06F1/26
摘要： A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the second clock distribution network, and a second phase synchronizer which provides a second output signal obtained by making the phase of the clock signal at a third point of the first clock distribution network coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the first clock distribution network. The semiconductor integrated circuit has a mode for changing a value of the second power supply voltage to a value which is different from a value of the first power supply voltage.
摘要翻译：一种半导体集成电路，包括提供有第一电源电压的第一电源区域，并具有第一时钟分配网络，提供有第二电源电压的第二电源区域，以及具有第二时钟分配网络的第一阶段同步器，其提供通过使第一时钟分配网络的第一点处的与时钟信号的相位一致的数据输入/输出的参考时钟信号的相位获得的第一输出信号到第二时钟信号的第二点时钟分配网络和第二相位同步器，其提供通过使第一时钟分配网络的第三点处的时钟信号的相位与第二时钟的第一点处的时钟信号的相位一致而获得的第二输出信号分销网络，到第一个时钟分配网络的第二点。半导体集成电路具有将第二电源电压的值改变为与第一电源电压的值不同的值的模式。

9. 发明授权

US07002871B2 Asynchronous pseudo SRAM and access method therefor 失效
标题翻译：异步伪SRAM及其访问方法
公开(公告)号：US07002871B2
公开(公告)日：2006-02-21
申请号：US10762459
申请日：2004-01-23
申请人： Yoshiaki Takeuchi , Kohei Oikawa
发明人： Yoshiaki Takeuchi , Kohei Oikawa
IPC分类号： G11C8/00
CPC分类号： G11C11/22
摘要： A semiconductor integrated circuit device includes an address buffer which receives an address signal that indicates an address of a memory cell array, a latch circuit which latches the data, and an address transition detection circuit which detects transition of the address. During the access operation of the memory cell array, an address at the operation start time is latched by the latch circuit. After the end of the operation of the memory cell array, an address that is currently input to the address buffer is latched by the latch circuit. If the received address signal is data different from the latch data, a control signal that controls the cycle operation of the memory cell array for a predetermined period is generated on the basis of the detection result from the address transition detection circuit.
摘要翻译：半导体集成电路装置包括地址缓冲器，其接收指示存储单元阵列的地址的地址信号，锁存数据的锁存电路以及检测地址的转换的地址转换检测电路。在存储单元阵列的访问操作期间，操作开始时刻的地址被锁存电路锁存。在存储单元阵列的操作结束之后，当前输入到地址缓冲器的地址被锁存电路锁存。如果接收到的地址信号是与锁存数据不同的数据，则根据来自地址转换检测电路的检测结果生成控制存储单元阵列的周期操作达预定周期的控制信号。

10. 发明申请

US20050057955A1 Semiconductor integrated circuit device and information storage method therefor 失效
标题翻译：半导体集成电路器件及其信息存储方法
公开(公告)号：US20050057955A1
公开(公告)日：2005-03-17
申请号：US10742837
申请日：2003-12-23
申请人： Kohei Oikawa
发明人： Kohei Oikawa
IPC分类号： G11C11/22 , G11C7/10 , G11C7/24
CPC分类号： G11C7/1045 , G11C7/24 , G11C11/22
摘要： A semiconductor integrated circuit device includes a cell array having a plurality of memory cells, a peripheral circuit which controls the cell array, and an operation information determination circuit. The operation information determination circuit determines either of a first operation mode in which one bit is stored by using one memory cell and a second operation mode in which one bit is stored by using two semiconductor memory cells, and supplies operation information to the peripheral circuit. The operation information determines which of the first and second operation modes is used to operate the cell array.
摘要翻译：半导体集成电路器件包括具有多个存储单元的单元阵列，控制单元阵列的外围电路和操作信息确定电路。操作信息确定电路通过使用一个存储单元来确定其中存储一位的第一操作模式和通过使用两个半导体存储单元存储一位的第二操作模式，并向外围电路提供操作信息。操作信息确定使用第一和第二操作模式中的哪一个来操作单元阵列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式