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1. 发明申请

US20080036048A1 Semiconductor junction device having reduced leakage current and method of forming same 审中-公开
标题翻译：具有减小的漏电流的半导体接合装置及其形成方法
公开(公告)号：US20080036048A1
公开(公告)日：2008-02-14
申请号：US11827594
申请日：2007-07-12
申请人： Sheng-Huei Dai , Ya-Chin King , Hai-Ning Wang , Ming-Tai Chiang
发明人： Sheng-Huei Dai , Ya-Chin King , Hai-Ning Wang , Ming-Tai Chiang
IPC分类号： H01L21/76 , H01L29/12
CPC分类号： H01L21/76216
摘要： A semiconductor junction device includes a semiconductor substrate of a first conductivity type and a junction layer formed on the substrate which has a second conductivity type. A field reducing region of the first conductivity type surrounds a periphery of the junction layer and extends under a peripheral portion of the junction layer. An insulating layer is provided on the field reducing region and a metal layer overlies the junction layer and the insulating layer.
摘要翻译：半导体结器件包括第一导电类型的半导体衬底和形成在具有第二导电类型的衬底上的接合层。第一导电类型的场减少区围绕结层的周边并在结层的周边部分的下方延伸。绝缘层设置在场致还区上，金属层覆盖在接合层和绝缘层上。

2. 发明申请

US20080036047A1 Low voltage transient voltage suppressor with reduced breakdown voltage 有权
标题翻译：具有降低击穿电压的低压瞬态电压抑制器
公开(公告)号：US20080036047A1
公开(公告)日：2008-02-14
申请号：US11827463
申请日：2007-07-11
申请人： Sheng-Huei Dai , Ya-Chin King , Hai-Ning Wang , Ming-Tai Chiang
发明人： Sheng-Huei Dai , Ya-Chin King , Hai-Ning Wang , Ming-Tai Chiang
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L29/861 , H01L29/66136
摘要： A semiconductor junction device includes a substrate of low resistivity semiconductor material having a preselected polarity. A tapered recess extends into the substrate and tapers inward as it extends downward from an upper surface of the substrate. A semiconductor layer is disposed within the recess and extends above the upper surface of the substrate. The semiconductor layer has a polarity opposite from that of the substrate. A metal layer overlies the semiconductor layer.
摘要翻译：半导体结器件包括具有预选极性的低电阻率半导体材料的衬底。锥形凹槽延伸到衬底中，并且从衬底的上表面向下延伸到内部渐缩。半导体层设置在凹槽内并在衬底的上表面上方延伸。半导体层的极性与基板的极性相反。金属层覆盖半导体层。

3. 发明授权

US07737533B2 Low voltage transient voltage suppressor with tapered recess extending into substrate of device allowing for reduced breakdown voltage 有权
标题翻译：低电压瞬态电压抑制器，具有延伸到器件基板的锥形凹槽，允许降低击穿电压
公开(公告)号：US07737533B2
公开(公告)日：2010-06-15
申请号：US11827463
申请日：2007-07-11
申请人： Sheng-Huei Dai , Ya-Chin King , Hai-Ning Wang , Ming-Tai Chiang
发明人： Sheng-Huei Dai , Ya-Chin King , Hai-Ning Wang , Ming-Tai Chiang
IPC分类号： H01L29/26
CPC分类号： H01L29/861 , H01L29/66136
摘要： A semiconductor junction device includes a substrate of low resistivity semiconductor material having a preselected polarity. A tapered recess extends into the substrate and tapers inward as it extends downward from an upper surface of the substrate. A semiconductor layer is disposed within the recess and extends above the upper surface of the substrate. The semiconductor layer has a polarity opposite from that of the substrate. A metal layer overlies the semiconductor layer.
摘要翻译：半导体结器件包括具有预选极性的低电阻率半导体材料的衬底。锥形凹槽延伸到衬底中，并且从衬底的上表面向下延伸到内部渐缩。半导体层设置在凹槽内并在衬底的上表面上方延伸。半导体层的极性与基板的极性相反。金属层覆盖半导体层。

4. 发明申请

US20070090360A1 Blanket implant diode 审中-公开
标题翻译：毯式植入二极管
公开(公告)号：US20070090360A1
公开(公告)日：2007-04-26
申请号：US11415522
申请日：2006-05-02
申请人： Sheng-Huei Dai , Ya-Chin King , Chun-Jen Huang , L.C. Kao
发明人： Sheng-Huei Dai , Ya-Chin King , Chun-Jen Huang , L.C. Kao
IPC分类号： H01L29/04 , H01L21/00 , H01L29/15 , H01L29/10 , H01L31/00 , H01L31/036
CPC分类号： H01L29/8611 , H01L29/66136
摘要： Blanket implant diode which can be used for transient voltage suppression having a P+ substrate implanted with an N-type dopant blanket implant near a top surface of the substrate, creating a P− region. An oxide mask is layered adjacent to and above the P− region. The oxide mask is partially etched away from a portion of the P− region, creating an etched region. An N-type main function implant is implanted into the etched region, creating an N+ region above the P+ substrate and adjacent the P− region. And, a metal is layered above the oxide mask in the etched region to form an electrode. Terminations may be attached electrically to both sides of the P-N junction. Methods of making and using the present invention and methods for transient voltage suppression are also provided.
摘要翻译：可以用于瞬态电压抑制的毯式注入二极管，其具有在衬底的顶表面附近注入N型掺杂剂覆盖层注入的P +衬底，形成P-区。在P区附近层叠氧化物掩模。氧化物掩模被部分地蚀刻离开P-区域的一部分，产生蚀刻区域。将N型主要功能植入物注入到蚀刻区域中，在P +衬底上方形成N +区域并邻近P-区域。并且，在蚀刻区域中的氧化物掩模上方形成金属以形成电极。端子可以电连接到P-N结的两侧。还提供了制造和使用本发明的方法和用于瞬态电压抑制的方法。

5. 发明授权

US08384155B2 Semiconductor capacitor 有权
标题翻译：半导体电容
公开(公告)号：US08384155B2
公开(公告)日：2013-02-26
申请号：US11697070
申请日：2007-04-05
申请人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
发明人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
IPC分类号： H01L29/94
CPC分类号： G11C17/04 , G11C2216/26 , H01L27/112 , H01L27/11206 , H01L29/94
摘要： A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned salicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.
摘要翻译：本文提供了具有栅极，栅极介电层，源极区域，漏极区域，电容器电介质层和导电插塞的一次性可编程存储器单元。栅介质层设置在基板上。栅极设置在栅极电介质层上。源极区域和漏极区域分别设置在栅极的侧面的基板中。电容器介质层设置在源极区域上。电容器介电层是电阻保护氧化物层或自对准的自对准硅化物阻挡层。导电插头设置在电容器电介质层上。导电插头用作电容器的第一电极，源区域用作电容器的第二电极。一次性可编程存储器（OTP）单元通过使电容器介质层击穿而被编程。

6. 发明申请

US20120257458A1 NON-VOLATILE SEMICONDUCTOR DEVICE, AND METHOD OF OPERATING THE SAME 有权
标题翻译：非挥发性半导体器件及其操作方法
公开(公告)号：US20120257458A1
公开(公告)日：2012-10-11
申请号：US13438642
申请日：2012-04-03
申请人： Chrong-Jung Lin , Ya-Chin King
发明人： Chrong-Jung Lin , Ya-Chin King
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： G11C16/16 , G11C16/0416 , H01L27/11521
摘要： A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a n-type floating gate, a coupling gate, a first n-type source/drain, a second n-type source/drain, a first contact plug and a second contact plug. The gate dielectric layer is formed on a p-type semiconductor substrate. The n-type floating gate is formed on the gate dielectric layer. The first n-type source/drain and the second n-type source/drain are formed in the p-type semiconductor substrate. The first and second contact plugs are formed on the first and second n-type source/drains respectively. The coupling gate consists essentially of a capacitor dielectric layer and a third contact plug, where the capacitor dielectric layer is formed on the n-type floating gate, and the third contact plug is formed on the capacitor dielectric layer.
摘要翻译：公开了一种非易失性半导体器件及其操作方法，其中非易失性半导体器件包括栅极电介质层，n型浮动栅极，耦合栅极，第一n型源极/漏极，第二n型源极/漏极，第一接触插塞和第二接触插塞。栅电介质层形成在p型半导体衬底上。 n型浮栅形成在栅介质层上。第一n型源极/漏极和第二n型源极/漏极形成在p型半导体衬底中。第一和第二接触塞分别形成在第一和第二n型源极/漏极上。耦合栅极基本上由电容器介电层和第三接触插塞构成，其中电容器电介质层形成在n型浮置栅极上，第三接触插塞形成在电容器介电层上。

7. 发明申请

US20120099361A1 SEMICONDUCTOR CAPACITOR, ONE TIME PROGRAMMABLE MEMORY CELL AND FABRICATING METHOD AND OPERATING METHOD THEREOF 审中-公开
标题翻译：半导体电容器，一次可编程存储器单元及其制作方法及其工作方法
公开(公告)号：US20120099361A1
公开(公告)日：2012-04-26
申请号：US13338632
申请日：2011-12-28
申请人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
发明人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
IPC分类号： G11C17/04
CPC分类号： G11C17/04 , G11C2216/26 , H01L27/112 , H01L27/11206 , H01L29/94
摘要： A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned silicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.
摘要翻译：本文提供了具有栅极，栅极介电层，源极区域，漏极区域，电容器电介质层和导电插塞的一次性可编程存储器单元。栅介质层设置在基板上。栅极设置在栅极电介质层上。源极区域和漏极区域分别设置在栅极的侧面的基板中。电容器介质层设置在源极区域上。电容器介电层是电阻保护氧化物层或自对准硅化物阻挡层。导电插头设置在电容器电介质层上。导电插头用作电容器的第一电极，源区域用作电容器的第二电极。一次性可编程存储器（OTP）单元通过使电容器介质层击穿而被编程。

8. 发明申请

US20110165727A1 METHOD OF FABRICATING PHOTO SENSOR 有权
标题翻译：制作照片传感器的方法
公开(公告)号：US20110165727A1
公开(公告)日：2011-07-07
申请号：US13045512
申请日：2011-03-10
申请人： Chien-Sen Weng , Chih-Wei Chao , Chrong-Jung Lin , Ya-Chin King
发明人： Chien-Sen Weng , Chih-Wei Chao , Chrong-Jung Lin , Ya-Chin King
IPC分类号： H01L31/18
CPC分类号： H01L31/153 , G02F2201/58
摘要： A method of fabricating a photo sensor includes the following steps. First, a substrate is provided, having a conductive layer, a buffer dielectric layer, a patterned semiconductor layer, a dielectric layer, and a planarization layer disposed thereon from bottom to top, wherein the patterned semiconductor layer comprises a first doped region, an intrinsic region, and a second doped region disposed in order. Then, the planarization layer is patterned to form an opening in the planarization layer to expose a portion of the dielectric layer, wherein the opening is positioned on the intrinsic region and portions of the first and the second doped regions. Thereafter, at least a patterned transparent conductive layer is formed in the opening, covering the boundary of the intrinsic region and the first doped region and the boundary of the intrinsic region and the second doped region.
摘要翻译：一种制造光传感器的方法包括以下步骤。首先，提供具有导电层，缓冲电介质层，图案化半导体层，电介质层和从底部到顶部设置在其上的平坦化层的衬底，其中所述图案化半导体层包括第一掺杂区域，区域，以及依次布置的第二掺杂区域。然后，对平坦化层进行图案化以在平坦化层中形成开口，以暴露电介质层的一部分，其中开口位于本征区域和第一和第二掺杂区域的部分上。此后，至少在开口中形成图案化的透明导电层，覆盖本征区域和第一掺杂区域以及本征区域和第二掺杂区域的边界的边界。

9. 发明授权

US07829920B2 Photo detector and a display panel having the same 有权
标题翻译：光检测器和具有该检测器的显示面板
公开(公告)号：US07829920B2
公开(公告)日：2010-11-09
申请号：US12175585
申请日：2008-07-18
申请人： An-Thung Cho , Chia-Tien Peng , Kun-Chih Lin , Wen-Jen Chiang , Chih-Yang Chen , Chrong-Jung Lin , Ya-Chin King , Chih-Wei Chao , Chien-Sen Weng , Feng-Yuan Gan
发明人： An-Thung Cho , Chia-Tien Peng , Kun-Chih Lin , Wen-Jen Chiang , Chih-Yang Chen , Chrong-Jung Lin , Ya-Chin King , Chih-Wei Chao , Chien-Sen Weng , Feng-Yuan Gan
IPC分类号： H01L31/062
CPC分类号： H01L31/153
摘要： A photo detector has a sensing TFT (thin film transistor) and a photodiode. The sensing TFT has a gate and a base. The photodiode has an intrinsic semiconductor region electrically connected to the gate and the base of the sensing TFT. The sensing TFT and the photodiode both have a structure comprising low temperature poly-silicon. A display panel contains the photo detector is also disclosed.
摘要翻译：光电检测器具有感测TFT（薄膜晶体管）和光电二极管。感测TFT具有栅极和基极。光电二极管具有与感测TFT的栅极和基极电连接的本征半导体区域。感测TFT和光电二极管都具有包括低温多晶硅的结构。还披露了包含光电检测器的显示面板。

10. 发明申请

US20090050906A1 Photo Detector and a Display Panel having the Same 有权
标题翻译：相片检测器和显示屏
公开(公告)号：US20090050906A1
公开(公告)日：2009-02-26
申请号：US12175585
申请日：2008-07-18
申请人： An-Thung Cho , Chia-Tien Peng , Kun-Chih Lin , Wen-Jen Chiang , Chih-Yang Chen , Chrong-Jung Lin , Ya-Chin King , Chih-Wei Chao , Chien-Sen Weng , Feng-Yuan Gan
发明人： An-Thung Cho , Chia-Tien Peng , Kun-Chih Lin , Wen-Jen Chiang , Chih-Yang Chen , Chrong-Jung Lin , Ya-Chin King , Chih-Wei Chao , Chien-Sen Weng , Feng-Yuan Gan
IPC分类号： H01L31/147 , H01L31/112
CPC分类号： H01L31/153
摘要： A photo detector has a sensing TFT (thin film transistor) and a photodiode. The sensing TFT has a gate and a base. The photodiode has an intrinsic semiconductor region electrically connected to the gate and the base of the sensing TFT. The sensing TFT and the photodiode both have a structure comprising low temperature poly-silicon. A display panel contains the photo detector is also disclosed.
摘要翻译：光电检测器具有感测TFT（薄膜晶体管）和光电二极管。感测TFT具有栅极和基极。光电二极管具有与感测TFT的栅极和基极电连接的本征半导体区域。感测TFT和光电二极管都具有包括低温多晶硅的结构。还披露了包含光电检测器的显示面板。

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