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1. 发明申请

US20050068069A1 INPUT/OUTPUT BUFFER 有权
标题翻译：输入/输出缓冲器
公开(公告)号：US20050068069A1
公开(公告)日：2005-03-31
申请号：US10673391
申请日：2003-09-30
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H03K19/003 , H03B1/00
CPC分类号： H03K19/00315
摘要： An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.
摘要翻译：一个输入/输出缓冲区。输入/输出电路具有耦合到I / O焊盘和浮动N阱区的传输端。 P栅极控制电路将第二栅极控制信号传送到第一PMOS晶体管的栅极。反馈检测装置耦合在传输终端和N阱控制电路之间，以根据I / O焊盘的输入电压输出反馈信号。 N阱控制电路根据从反馈检测装置输出的反馈信号，调整第一PMOS晶体管的N阱区域的电压电平。

2. 发明申请

US20050128670A1 Input/output buffer protection circuit 有权
标题翻译：输入/输出缓冲保护电路
公开(公告)号：US20050128670A1
公开(公告)日：2005-06-16
申请号：US10735324
申请日：2003-12-12
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H01L27/02 , H03K19/003 , H02H3/20
CPC分类号： H03K19/00315 , H01L27/0266
摘要： An input/output buffer protection circuit, which comprises an I/O pad, an I/O buffer, an n-well control circuit, a gate control circuit, and a protection component. The I/O buffer includes a PMOS transistor and a NMOS transistor. The n-well control circuit is coupled to an n-well of the PMOS transistor. When an input voltage higher than a source voltage is applied, voltage at the n-well of the PMOS is increased by the n-well control circuit to the input voltage level. The gate control circuit is coupled to the gate terminal of the PMOS transistor and the input/output pad. When an input voltage higher than a source voltage is applied, voltage at the gate terminal of the PMOS is increased by the gate control circuit to the source voltage level. Wherein the gate control circuit comprises a transistor and the transistor transfers a high potential control voltage to the gate of the PMOS transistor in output mode. The protection component is coupled between the gate of the transistor and the I/O pad to generate a voltage drop down path and block the I/O pad signal from flowing back to the gate of the transistor.
摘要翻译：输入/输出缓冲器保护电路，其包括I / O焊盘，I / O缓冲器，n阱控制电路，栅极控制电路和保护部件。 I / O缓冲器包括PMOS晶体管和NMOS晶体管。 n阱控制电路耦合到PMOS晶体管的n阱。当施加高于源电压的输入电压时，PMOS的n阱处的电压由n阱控制电路增加到输入电压电平。栅极控制电路耦合到PMOS晶体管的栅极端子和输入/输出焊盘。当施加高于源极电压的输入电压时，PMOS栅极端子处的电压由栅极控制电路增加到源极电压电平。其中栅极控制电路包括晶体管，并且晶体管在输出模式下将高电位控制电压传送到PMOS晶体管的栅极。保护元件耦合在晶体管的栅极和I / O焊盘之间，以产生电压降降路径，并阻止I / O焊盘信号流回晶体管的栅极。

3. 发明授权

US07046493B2 Input/output buffer protection circuit 有权
标题翻译：输入/输出缓冲保护电路
公开(公告)号：US07046493B2
公开(公告)日：2006-05-16
申请号：US10735324
申请日：2003-12-12
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H02H9/00
CPC分类号： H03K19/00315 , H01L27/0266
摘要： An input/output buffer protection circuit, which comprises an I/O pad, an I/O buffer, an n-well control circuit, a gate control circuit, and a protection component. The I/O buffer includes a PMOS transistor and a NMOS transistor. The n-well control circuit is coupled to an n-well of the PMOS transistor. When an input voltage higher than a source voltage is applied, voltage at the n-well of the PMOS is increased by the n-well control circuit to the input voltage level. The gate control circuit is coupled to the gate terminal of the PMOS transistor and the input/output pad. When an input voltage higher than a source voltage is applied, voltage at the gate terminal of the PMOS is increased by the gate control circuit to the source voltage level. Wherein the gate control circuit comprises a transistor and the transistor transfers a high potential control voltage to the gate of the PMOS transistor in output mode. The protection component is coupled between the gate of the transistor and the I/O pad to generate a voltage drop down path and block the I/O pad signal from flowing back to the gate of the transistor.
摘要翻译：输入/输出缓冲器保护电路，其包括I / O焊盘，I / O缓冲器，n阱控制电路，栅极控制电路和保护部件。 I / O缓冲器包括PMOS晶体管和NMOS晶体管。 n阱控制电路耦合到PMOS晶体管的n阱。当施加高于源电压的输入电压时，PMOS的n阱处的电压由n阱控制电路增加到输入电压电平。栅极控制电路耦合到PMOS晶体管的栅极端子和输入/输出焊盘。当施加高于源极电压的输入电压时，PMOS栅极端子处的电压由栅极控制电路增加到源极电压电平。其中栅极控制电路包括晶体管，并且晶体管在输出模式下将高电位控制电压传送到PMOS晶体管的栅极。保护元件耦合在晶体管的栅极和I / O焊盘之间，以产生电压降降路径，并阻止I / O焊盘信号流回晶体管的栅极。

4. 发明授权

US06882188B1 Input/output buffer 有权
标题翻译：输入/输出缓冲器
公开(公告)号：US06882188B1
公开(公告)日：2005-04-19
申请号：US10673391
申请日：2003-09-30
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H03K19/003 , H03B1/00
CPC分类号： H03K19/00315
摘要： An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.
摘要翻译：一个输入/输出缓冲区。输入/输出电路具有耦合到I / O焊盘和浮动N阱区的传输端。 P栅极控制电路将第二栅极控制信号传送到第一PMOS晶体管的栅极。反馈检测装置耦合在传输终端和N阱控制电路之间，以根据I / O焊盘的输入电压输出反馈信号。 N阱控制电路根据从反馈检测装置输出的反馈信号，调整第一PMOS晶体管的N阱区域的电压电平。

5. 发明授权

US06861874B1 Input/output buffer 有权
标题翻译：输入/输出缓冲器
公开(公告)号：US06861874B1
公开(公告)日：2005-03-01
申请号：US10679399
申请日：2003-10-07
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315
摘要： An input/output buffer. An input/output circuit is composed of a first PMOS transistor and a first NMOS transistor, has an I/O port coupled to an I/O pad, and a N-well region. An N-well control circuit controls the voltage level at the N-well region of the first PMOS transistor according to input signals at the I/O pad. A P-gate control circuit receives a second gate control signal and outputs to the gate of the first PMOS transistor. The P-gate control circuit is composed of a transmission gate and a third PMOS transistor. The transmission gate and the third PMOS transistor do not have to follow the design rule for ESD, and the wafer area required for the P-gate control circuit can be decreased because the P-gate control circuit is not directly connected to the I/O pad.
摘要翻译：一个输入/输出缓冲区。输入/输出电路由第一PMOS晶体管和第一NMOS晶体管组成，具有耦合到I / O焊盘的I / O端口和N阱区域。 N阱控制电路根据I / O焊盘上的输入信号来控制第一PMOS晶体管的N阱区域的电压电平。 P栅极控制电路接收第二栅极控制信号并输出到第一PMOS晶体管的栅极。 P栅极控制电路由传输栅极和第三PMOS晶体管构成。传输栅极和第三PMOS晶体管不必遵循ESD的设计规则，因为P栅极控制电路不直接连接到I / O，所以P栅极控制电路所需的晶片面积可以减小垫。

6. 发明申请

US20100237509A1 IO CELL WITH MULTIPLE IO PORTS AND RELATED TECHNIQUES FOR LAYOUT AREA SAVING 有权
标题翻译：具有多个IO端口的IO单元和用于布局区域的相关技术节省
公开(公告)号：US20100237509A1
公开(公告)日：2010-09-23
申请号：US12697582
申请日：2010-02-01
申请人： Jeng-Huang WU , Hung-Yi Chang , Chu Huang
发明人： Jeng-Huang WU , Hung-Yi Chang , Chu Huang
IPC分类号： H01L23/485 , H05K7/00
CPC分类号： H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/01046 , H01L2924/01055 , H01L2924/01082 , H01L2924/01084 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving.
摘要翻译：提供了具有多个IO端口和相关技术的IO单元。 IO单元具有用于发送相同IO引脚的信号的多个IO端口，并且每个IO端口对应于用于容纳IO垫的预定区域，其中多个IO端口的多个预定区域中的至少一个部分地与 IO单元的有源电路布局区域。在芯片中，如果给定IO单元具有与另一相邻IO单元的IO垫位置重叠的IO端口的预定区域，则选择另一IO端口的预定区域以实现给定IO单元的IO垫，可以更紧凑地布置IO单元，以节省芯片布局面积。

7. 发明授权

US08169068B2 IO cell with multiple IO ports and related techniques for layout area saving 有权
标题翻译：具有多个IO端口的IO单元和相关技术，用于布局区域的保存
公开(公告)号：US08169068B2
公开(公告)日：2012-05-01
申请号：US12697582
申请日：2010-02-01
申请人： Jeng-Huang Wu , Hung-Yi Chang , Chun Huang
发明人： Jeng-Huang Wu , Hung-Yi Chang , Chun Huang
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/01046 , H01L2924/01055 , H01L2924/01082 , H01L2924/01084 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving.
摘要翻译：提供了具有多个IO端口和相关技术的IO单元。 IO单元具有用于发送相同IO引脚的信号的多个IO端口，并且每个IO端口对应于用于容纳IO垫的预定区域，其中多个IO端口的多个预定区域中的至少一个部分地与 IO单元的有源电路布局区域。在芯片中，如果给定IO单元具有与另一相邻IO单元的IO垫位置重叠的IO端口的预定区域，则选择另一IO端口的预定区域以实现给定IO单元的IO垫，可以更紧凑地布置IO单元，以节省芯片布局面积。

8. 发明授权

US08475243B2 Coin dispensing and storing device 有权
标题翻译：硬币分配和存储设备
公开(公告)号：US08475243B2
公开(公告)日：2013-07-02
申请号：US13585686
申请日：2012-08-14
申请人： Hung-Yi Chang
发明人： Hung-Yi Chang
IPC分类号： G07D1/00
CPC分类号： G07D1/00
摘要： A coin dispensing and storing device includes a body, coin collecting tubes, a left rotatable support, a pivotal plate and a right rotatable support. Coins are received in the coin collecting tubes. The left rotatable support is pivotally connected to one side of the body. The left rotatable support allows a portion of the coin collecting tubes to be disposed therein. The pivotal plate is pivotally connected to the other side of the body. The right rotatable support is connected to the pivotal plate. The right rotatable support allows the remaining portion of the coin collecting tubes to be disposed therein. The left and the right rotatable supports can be pivotally received in or rotated to the outside of the body. With this arrangement, the operation is labor-saving. Further, the force exerting on the respective rotatable supports can be distributed efficiently to reduce the generation of damage and deformation.
摘要翻译：硬币分配和存储装置包括主体，硬币收集管，左旋转支撑件，枢转板和右旋转支撑件。硬币收集在硬币收集管中。左旋转支撑件枢转地连接到主体的一侧。左旋转支撑件允许硬币收集管的一部分设置在其中。枢转板枢转地连接到主体的另一侧。右旋转支撑件连接到枢转板。正确的可旋转支撑件允许将硬币收集管的剩余部分设置在其中。左右可旋转支撑件可以枢转地容纳在身体的外部或旋转到身体的外部。通过这种安排，操作省力。此外，可以有效地分配施加在相应的可旋转支撑件上的力，以减少损坏和变形的产生。

9. 发明授权

US08445311B2 Method of fabricating a differential doped solar cell 有权
标题翻译：制造差分掺杂太阳能电池的方法
公开(公告)号：US08445311B2
公开(公告)日：2013-05-21
申请号：US13303126
申请日：2011-11-22
申请人： Chi-Hsiung Chang , Kuan-Lun Chang , Hung-Yi Chang , Yi-Min Pan , Jun-Min Wu , Ying-Yen Chiu
发明人： Chi-Hsiung Chang , Kuan-Lun Chang , Hung-Yi Chang , Yi-Min Pan , Jun-Min Wu , Ying-Yen Chiu
IPC分类号： H01L21/00
CPC分类号： H01L31/18 , H01L31/022425 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a differential doped solar cell is provided. The method comprises the steps of (a) providing a light doped semiconductor substrate; (b) forming a heavy doped layer having the same type of dopant used in step (a) on a front surface of the semiconductor substrate; and (c) forming an emitter layer having a different type of dopant used in step (a) on a surface of the heavy doped layer to constitute a p-n junction with the heavy doped layer.
摘要翻译：提供了一种制造差分掺杂太阳能电池的方法。该方法包括以下步骤：（a）提供掺杂光的半导体衬底; （b）在半导体衬底的前表面上形成具有与步骤（a）中使用的相同类型掺杂剂的重掺杂层; 和（c）在重掺杂层的表面上形成具有在步骤（a）中使用的不同类型的掺杂剂的发射极层，以与重掺杂层构成p-n结。

10. 发明授权

US08088294B2 Method for manufacturing printed circuit boards 有权
标题翻译：制造印刷电路板的方法
公开(公告)号：US08088294B2
公开(公告)日：2012-01-03
申请号：US12110542
申请日：2008-04-28
申请人： Tso-Hung Yeh , Hung-Yi Chang , Chia-Cheng Chen
发明人： Tso-Hung Yeh , Hung-Yi Chang , Chia-Cheng Chen
IPC分类号： H01B13/00
CPC分类号： H05K3/064 , H05K3/382 , H05K2203/095
摘要： An exemplary method for manufacturing printed circuit boards is provided. In the method, a copper clad substrate having a copper layer thereon is provided. A surface of the copper layer is roughened by applying an atmospheric pressure plasma thereto. A photoresist layer is formed on the roughened surface of the copper layer. The photoresist layer is exposed. The photoresist layer is developed to form a patterned photoresist layer, thereby exposing portions of the copper layer. The exposed portions of the copper layer exposed are removed so that the remaining portions of the copper layer form electrical traces. The patterned photoresist layer is removed.
摘要翻译：提供了制造印刷电路板的示例性方法。在该方法中，提供了具有铜层的铜包覆基板。通过向其施加大气压等离子体使铜层的表面变粗糙。在铜层的粗糙化表面上形成光致抗蚀剂层。曝光光致抗蚀剂层。显影光致抗蚀剂层以形成图案化的光致抗蚀剂层，从而暴露铜层的部分。去除暴露的铜层的暴露部分，使得铜层的其余部分形成电迹线。去除图案化的光致抗蚀剂层。

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