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1. 发明申请

US20120164779A1 METHOD OF FABRICATING A DIFFERENTIAL DOPED SOLAR CELL 有权
标题翻译：制造差异放电太阳能电池的方法
公开(公告)号：US20120164779A1
公开(公告)日：2012-06-28
申请号：US13303126
申请日：2011-11-22
申请人： Chi-Hsiung CHANG , Kuan-Lun Chang , Hung-Yi Chang , Yi-Min Pan , Jun-Min Wu , Ying-Yen Chiu
发明人： Chi-Hsiung CHANG , Kuan-Lun Chang , Hung-Yi Chang , Yi-Min Pan , Jun-Min Wu , Ying-Yen Chiu
IPC分类号： H01L31/18
CPC分类号： H01L31/18 , H01L31/022425 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a differential doped solar cell is provided. The method comprises the steps of (a) providing a light doped semiconductor substrate; (b) forming a heavy doped layer having the same type of dopant used in step (a) on a front surface of the semiconductor substrate; and (c) forming an emitter layer having a different type of dopant used in step (a) on a surface of the heavy doped layer to constitute a p-n junction with the heavy doped layer.
摘要翻译：提供了一种制造差分掺杂太阳能电池的方法。该方法包括以下步骤：（a）提供光掺杂半导体衬底; （b）在半导体衬底的前表面上形成具有与步骤（a）中使用的相同类型掺杂剂的重掺杂层; 和（c）在重掺杂层的表面上形成具有在步骤（a）中使用的不同类型的掺杂剂的发射极层，以与重掺杂层构成p-n结。

2. 发明授权

US08445311B2 Method of fabricating a differential doped solar cell 有权
标题翻译：制造差分掺杂太阳能电池的方法
公开(公告)号：US08445311B2
公开(公告)日：2013-05-21
申请号：US13303126
申请日：2011-11-22
申请人： Chi-Hsiung Chang , Kuan-Lun Chang , Hung-Yi Chang , Yi-Min Pan , Jun-Min Wu , Ying-Yen Chiu
发明人： Chi-Hsiung Chang , Kuan-Lun Chang , Hung-Yi Chang , Yi-Min Pan , Jun-Min Wu , Ying-Yen Chiu
IPC分类号： H01L21/00
CPC分类号： H01L31/18 , H01L31/022425 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a differential doped solar cell is provided. The method comprises the steps of (a) providing a light doped semiconductor substrate; (b) forming a heavy doped layer having the same type of dopant used in step (a) on a front surface of the semiconductor substrate; and (c) forming an emitter layer having a different type of dopant used in step (a) on a surface of the heavy doped layer to constitute a p-n junction with the heavy doped layer.
摘要翻译：提供了一种制造差分掺杂太阳能电池的方法。该方法包括以下步骤：（a）提供掺杂光的半导体衬底; （b）在半导体衬底的前表面上形成具有与步骤（a）中使用的相同类型掺杂剂的重掺杂层; 和（c）在重掺杂层的表面上形成具有在步骤（a）中使用的不同类型的掺杂剂的发射极层，以与重掺杂层构成p-n结。

3. 发明申请

US20060063389A1 Structure having a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology 有权
标题翻译：具有BiCMOS / CMOS技术的浅沟槽深沟槽隔离区域的结构
公开(公告)号：US20060063389A1
公开(公告)日：2006-03-23
申请号：US11272259
申请日：2005-11-10
申请人： Kuan-Lun Chang , Ruey-Hsin Liu , Tsyr-Shyang Liou , Chih-Min Chiang , Jun-Lin Tsai
发明人： Kuan-Lun Chang , Ruey-Hsin Liu , Tsyr-Shyang Liou , Chih-Min Chiang , Jun-Lin Tsai
IPC分类号： H01L21/31
CPC分类号： H01L21/76232 , H01L21/763
摘要： A structure having a shallow trench-deep trench isolation region for a semiconductor device is provided.
摘要翻译：提供一种具有用于半导体器件的浅沟槽 - 深沟槽隔离区域的结构。

4. 发明申请

US20060063349A1 Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology 有权
标题翻译：为BiCMOS / CMOS技术形成浅沟槽深沟槽隔离区域的方法
公开(公告)号：US20060063349A1
公开(公告)日：2006-03-23
申请号：US11272260
申请日：2005-11-10
申请人： Kuan-Lun Chang , Ruey-Hsin Liu , Tsyr-Shyang Liou , Chih-Min Chiang , Jun-Lin Tsai
发明人： Kuan-Lun Chang , Ruey-Hsin Liu , Tsyr-Shyang Liou , Chih-Min Chiang , Jun-Lin Tsai
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L21/763
摘要： A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.
摘要翻译：提供了一种形成用于半导体器件的浅沟槽 - 深沟槽隔离的方法。

5. 发明申请

US20050121744A1 High density MIM capacitor structure and fabrication process 有权
标题翻译：高密度MIM电容器结构及制造工艺
公开(公告)号：US20050121744A1
公开(公告)日：2005-06-09
申请号：US10729034
申请日：2003-12-04
申请人： Kuan-Lun Chang , Chuan-Ying Lee , Chun-Hon Chen
发明人： Kuan-Lun Chang , Chuan-Ying Lee , Chun-Hon Chen
IPC分类号： H01L21/02 , H01L23/522 , H01L27/08 , H01L29/00
CPC分类号： H01L28/40 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： A stacked integrated circuit (IC) MIM capacitor structure and method for forming the same the MIM capacitor structure including a first MIM capacitor structure formed in a first IMD layer comprising an first upper and first lower electrode portions; at least a second MIM capacitor structure arranged in stacked relationship in an overlying IMD layer comprising a second upper electrode and second lower electrode to form an MIM capacitor stack; wherein, the first lower electrode is arranged in common electrical signal communication comprising metal filled vias with the second upper electrode and the first upper electrode is arranged in common electrical signal communication with the second lower electrode.
摘要翻译：一种用于形成MIM电容器结构的叠层集成电路（IC）MIM电容器结构及方法，包括形成在包括第一上电极部分和第一下电极部分的第一IMD层中的第一MIM电容器结构; 至少第二MIM电容器结构，以层叠的关系布置在包括第二上电极和第二下电极的上覆IMD层中，以形成MIM电容器堆叠; 其中，所述第一下部电极布置成共同的电信号通信，包括金属填充的通孔与所述第二上部电极和所述第一上部电极被布置成与所述第二下部电极共同的电信号通信。

6. 发明授权

US06352901B1 Method of fabricating a bipolar junction transistor using multiple selectively implanted collector regions 有权
标题翻译：使用多个选择性注入的集电极区域制造双极结型晶体管的方法
公开(公告)号：US06352901B1
公开(公告)日：2002-03-05
申请号：US09534164
申请日：2000-03-24
申请人： Kuan-Lun Chang
发明人： Kuan-Lun Chang
IPC分类号： H01L2120
CPC分类号： H01L29/66272 , H01L29/0821
摘要： A process for fabricating a bipolar junction transistor, featuring the use of multiple self-aligned collector regions, used to limit the width of the base region of the transistor, has been developed. The self-aligned collector regions are formed via multiple ion implantation procedures, performed through, and self-aligned to, an overlying emitter opening, in an oxide layer. The self-aligned collector regions, completely fill the space in the lighter doped collector region, located between the overlying base region, and the underlying subcollector region.
摘要翻译：已经开发了用于制造双极结型晶体管的工艺，其特征在于使用多个自对准的集电极区域来限制晶体管的基极区域的宽度。经由多个离子注入程序形成自对准的集电极区域，其通过氧化物层中的上层发射极开口进行和自对准。自对准的集电极区域完全填充位于覆盖的基极区域和下面的子集电极区域之间的较轻掺杂的集电极区域中的空间。

7. 发明授权

US07250344B2 Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology 有权
标题翻译：为BiCMOS / CMOS技术形成浅沟槽深沟槽隔离区域的方法
公开(公告)号：US07250344B2
公开(公告)日：2007-07-31
申请号：US11272260
申请日：2005-11-10
申请人： Kuan-Lun Chang , Ruey-Hsin Liu , Tsyr-Shyang Liou , Chih-Min Chiang , Jun-Lin Tsai
发明人： Kuan-Lun Chang , Ruey-Hsin Liu , Tsyr-Shyang Liou , Chih-Min Chiang , Jun-Lin Tsai
IPC分类号： H01L21/336
CPC分类号： H01L21/76232 , H01L21/763
摘要： A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.
摘要翻译：提供了一种形成用于半导体器件的浅沟槽 - 深沟槽隔离的方法。

8. 发明申请

US20060278928A1 Semiconductor layout structure for ESD protection circuits 有权
标题翻译： ESD保护电路的半导体布局结构
公开(公告)号：US20060278928A1
公开(公告)日：2006-12-14
申请号：US11152440
申请日：2005-06-14
申请人： Yi-Hsun Wu , Kuan-Lun Chang , Chuan-Ying Lee , Jian-Hsing Lee
发明人： Yi-Hsun Wu , Kuan-Lun Chang , Chuan-Ying Lee , Jian-Hsing Lee
IPC分类号： H01L23/62
CPC分类号： H01L27/0262
摘要： A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event. The first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event.
摘要翻译：公开了一种用于静电放电（ESD）保护电路的半导体布局结构。半导体布局结构包括第一区域，其中构造一个或多个器件用作可控硅整流器，以及第二区域，其中构造至少一个器件用作触发源，该触发源提供触发电流触发可控硅整流器，以在ESD事件期间耗散ESD电荷。第一区域和第二区域彼此相邻放置，而不会在其间物理地插入或电连接电阻区域，使得在ESD事件期间由可控硅整流器接收的触发电流增加。

9. 发明授权

US06303419B1 Method for fabricating a BiCMOS device featuring twin wells and an N type epitaxial layer 有权
标题翻译：用于制造具有双阱和N型外延层的BiCMOS器件的方法
公开(公告)号：US06303419B1
公开(公告)日：2001-10-16
申请号：US09534165
申请日：2000-03-24
申请人： Kuan-Lun Chang , Bing-Yue Tsui
发明人： Kuan-Lun Chang , Bing-Yue Tsui
IPC分类号： H01L218238
CPC分类号： H01L21/8249
摘要： A process for fabricating a BiCMOS device, on a semiconductor substrate, featuring PFET and NFET devices, and an NPN bipolar junction transistor, has been developed. The process features the integration, or the sharing of process steps, used for both the CMOS and bipolar devices, such as the creation of an N type buried layer, used in one region for isolation of PFET devices, and used in a second region, of the semiconductor substrate, as a subcollector region, for the bipolar device. Features of the BiCMOS process include the formation of N well, and P well regions, for CMOS device, as well as the use of an epitaxial silicon layer, to allow optimum bipolar characteristics to be achieved.
摘要翻译：已经开发了在具有PFET和NFET器件的半导体衬底以及NPN双极结型晶体管上制造BiCMOS器件的工艺。该方法具有用于CMOS和双极器件的集成或共享工艺步骤，例如在用于隔离PFET器件的一个区域中使用并用于第二区域中的N型掩埋层的产生，作为双极性器件的子集电极区域。 BiCMOS工艺的特征包括形成N阱，用于CMOS器件的P阱区，以及使用外延硅层，以实现最佳的双极特性。

10. 发明授权

US07317221B2 High density MIM capacitor structure and fabrication process 有权
标题翻译：高密度MIM电容器结构及制造工艺
公开(公告)号：US07317221B2
公开(公告)日：2008-01-08
申请号：US10729034
申请日：2003-12-04
申请人： Kuan-Lun Chang , Chuan-Ying Lee , Chun-Hon Chen
发明人： Kuan-Lun Chang , Chuan-Ying Lee , Chun-Hon Chen
IPC分类号： H01L29/72
CPC分类号： H01L28/40 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： A stacked integrated circuit (IC) MIM capacitor structure and method for forming the same the MIM capacitor structure including a first MIM capacitor structure formed in a first IMD layer comprising an first upper and first lower electrode portions; at least a second MIM capacitor structure arranged in stacked relationship in an overlying IMD layer comprising a second upper electrode and second lower electrode to form an MIM capacitor stack; wherein, the first lower electrode is arranged in common electrical signal communication comprising metal filled vias with the second upper electrode and the first upper electrode is arranged in common electrical signal communication with the second lower electrode.
摘要翻译：一种用于形成MIM电容器结构的叠层集成电路（IC）MIM电容器结构及方法，包括形成在包括第一上电极部分和第一下电极部分的第一IMD层中的第一MIM电容器结构; 至少第二MIM电容器结构，以层叠的关系布置在包括第二上电极和第二下电极的上覆IMD层中，以形成MIM电容器堆叠; 其中，所述第一下部电极布置成共同的电信号通信，包括金属填充的通孔与所述第二上部电极和所述第一上部电极被布置成与所述第二下部电极共同的电信号通信。

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