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1. 发明申请

US20090277792A1 Method for concentrating charged particles and apparatus thereof 审中-公开
标题翻译：浓缩带电粒子的方法及其装置
公开(公告)号：US20090277792A1
公开(公告)日：2009-11-12
申请号：US12383893
申请日：2009-03-30
申请人： Shau-Chun Wang , Hsueh-Chia Chang , Hsiao-Ping Chen , Hsien-Hung Wei , Chun-Ching Yu , Min-Hsuan Tsai
发明人： Shau-Chun Wang , Hsueh-Chia Chang , Hsiao-Ping Chen , Hsien-Hung Wei , Chun-Ching Yu , Min-Hsuan Tsai
IPC分类号： G01N27/447 , G01N27/453
CPC分类号： B03C5/02
摘要： The present invention discloses a method for concentrating charged particles and an apparatus thereof. The method comprises: providing a substrate comprising a reservoir; disposing a conducting granule in the reservoir, the conducting granule being negatively charged or positively charged and comprising nano-pores or nano-channels capable of permitting ion permeation; disposing a buffer solution in the reservoir, the buffer solution comprising counter-ions having an opposite electric property to the conducting granule; adding the charged particles into the buffer solution, the charged particles being co-ions having an identical electric property as the conducting granule; and applying an external electric field on the conducting granule. While the external electric field is applied on the conducting granule, the counter-ions exit from the nano-pores or nano-channels and have a nonuniform concentration on a surface of the conducting granule such that a transient ion super-concentration phenomenon occurs at an ejecting pole on the conducting granule. Hence the present invention has potential application in bead-based molecular assays.
摘要翻译：本发明公开了一种用于浓缩带电粒子的方法及其装置。该方法包括：提供包括储存器的基底; 在储存器中设置导电颗粒，导电颗粒带负电荷或带正电荷，并包含能够允许离子渗透的纳米孔或纳米通道; 在储存器中设置缓冲溶液，所述缓冲溶液包含与导电颗粒具有相反电性质的抗衡离子; 将带电粒子加入到缓冲溶液中，带电粒子是与导电颗粒具有相同电性质的共离子; 并在导电颗粒上施加外部电场。当外部电场施加在导电颗粒上时，抗衡离子从纳米孔或纳米通道离开，并且在导电颗粒的表面上具有不均匀的浓度，使得瞬时离子超浓度现象发生在在导电颗粒上喷射极。因此，本发明在基于珠的分子测定中具有潜在的应用。

2. 发明授权

US08026549B2 LDMOS with N-type isolation ring and method of fabricating the same 有权
标题翻译：具有N型隔离环的LDMOS及其制造方法
公开(公告)号：US08026549B2
公开(公告)日：2011-09-27
申请号：US12263108
申请日：2008-10-31
申请人： Chin-Lung Chen , Chun-Ching Yu , Jung-Ching Chen , Ming-Tsung Tung
发明人： Chin-Lung Chen , Chun-Ching Yu , Jung-Ching Chen , Ming-Tsung Tung
IPC分类号： H01L29/66
CPC分类号： H01L21/823892 , H01L21/823857 , H01L21/823878 , H01L27/092 , H01L27/0922
摘要： A semiconductor device and an IC chip are described. The deep N-well region is configured in a substrate. The P-well region surrounds a periphery of the deep N-well region. The gate structure is disposed on the substrate of the deep N-well region. The P-body region is configured in the deep N-well region at one side of the gate structure. The first N-type doped region is configured in the P-body region. The second N-type doped region is configured pin the deep N-well region at the other side of the gate structure. The first isolation structure is disposed between the gate structure and the second N-type doped region. The N-type isolation ring is configured in the deep N-well region and corresponding to an edge of the deep N-well region, wherein a doping concentration of the N-type isolation ring is higher than that of the deep N-well region.
摘要翻译：描述半导体器件和IC芯片。深N阱区配置在基板中。 P阱区域围绕深N阱区域的周边。栅极结构设置在深N阱区域的衬底上。 P体区域配置在栅极结构一侧的深N阱区域。第一N型掺杂区域配置在P体区域中。第二N型掺杂区域被配置为在栅极结构的另一侧上的深N阱区域。第一隔离结构设置在栅极结构和第二N型掺杂区之间。 N型隔离环配置在深N阱区并对应于深N阱区的边缘，其中N型隔离环的掺杂浓度高于深N阱区的掺杂浓度。

3. 发明申请

US20080237740A1 SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080237740A1
公开(公告)日：2008-10-02
申请号：US11693437
申请日：2007-03-29
申请人： Jung-Ching Chen , Chun-Ching Yu
发明人： Jung-Ching Chen , Chun-Ching Yu
IPC分类号： H01L27/088 , H01L21/77
CPC分类号： H01L21/823857 , H01L21/823814 , H01L27/0922
摘要： A method of manufacturing a semiconductor device is provided. First, a substrate is provided. The substrate includes a high-voltage device region and a low-voltage device region. The high-voltage device region has a source/drain predetermined region, a pick-up predetermined region and a channel predetermined region. A first dielectric layer is formed on the substrate. Then, the first dielectric layer in the low-voltage device region is removed along with the first dielectric layer in the source/drain predetermined region and the pick-up predetermined region. Afterwards, a second dielectric layer is formed in the low-voltage device region. The thickness of the second dielectric layer is smaller than the thickness of the first dielectric layer. Then, gates are formed in the channel predetermined region and the low-voltage device region respectively. Next, a source/drain region is formed in the substrate of the source/drain predetermined region.
摘要翻译：提供一种制造半导体器件的方法。首先，提供基板。衬底包括高电压器件区域和低电压器件区域。高压器件区域具有源极/漏极预定区域，拾取预定区域和沟道预定区域。在基板上形成第一电介质层。然后，在源极/漏极预定区域和拾取预定区域中，与第一电介质层一起去除低压器件区域中的第一电介质层。之后，在低电压器件区域形成第二电介质层。第二电介质层的厚度小于第一电介质层的厚度。然后，分别在沟道预定区域和低压器件区域中形成栅极。接下来，在源极/漏极预定区域的衬底中形成源极/漏极区域。

4. 发明申请

US20100109081A1 SEMICONDUCTOR DEVICE AND IC CHIP 有权
标题翻译：半导体器件和IC芯片
公开(公告)号：US20100109081A1
公开(公告)日：2010-05-06
申请号：US12263108
申请日：2008-10-31
申请人： Chin-Lung Chen , Chun-Ching Yu , Jung-Ching Chen , Ming-Tsung Tung
发明人： Chin-Lung Chen , Chun-Ching Yu , Jung-Ching Chen , Ming-Tsung Tung
IPC分类号： H01L27/088
CPC分类号： H01L21/823892 , H01L21/823857 , H01L21/823878 , H01L27/092 , H01L27/0922
摘要： A semiconductor device and an IC chip are described. The deep N-well region is configured in a substrate. The P-well region surrounds a periphery of the deep N-well region. The gate structure is disposed on the substrate of the deep N-well region. The P-body region is configured in the deep N-well region at one side of the gate structure. The first N-type doped region is configured in the P-body region. The second N-type doped region is configured pin the deep N-well region at the other side of the gate structure. The first isolation structure is disposed between the gate structure and the second N-type doped region. The N-type isolation ring is configured in the deep N-well region and corresponding to an edge of the deep N-well region, wherein a doping concentration of the N-type isolation ring is higher than that of the deep N-well region.
摘要翻译：描述半导体器件和IC芯片。深N阱区配置在基板中。 P阱区域围绕深N阱区域的周边。栅极结构设置在深N阱区域的衬底上。 P体区域配置在栅极结构一侧的深N阱区域。第一N型掺杂区域配置在P体区域中。第二N型掺杂区域被配置为在栅极结构的另一侧上的深N阱区域。第一隔离结构设置在栅极结构和第二N型掺杂区之间。 N型隔离环配置在深N阱区并对应于深N阱区的边缘，其中N型隔离环的掺杂浓度高于深N阱区的掺杂浓度。

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