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1. 发明授权

US06608362B1 Method and device for reducing capacitive and magnetic effects from a substrate by using a schottky diode under passive components 失效
标题翻译：用于通过在被动元件下使用肖特基二极管来降低基板的电容和磁效应的方法和装置
公开(公告)号：US06608362B1
公开(公告)日：2003-08-19
申请号：US10224150
申请日：2002-08-20
申请人： Shao Kai , Sanford Chu , Chit Hwei Ng , Jia Zhen Zheng , Sia Choon Beng , Chew Kok Wai
发明人： Shao Kai , Sanford Chu , Chit Hwei Ng , Jia Zhen Zheng , Sia Choon Beng , Chew Kok Wai
IPC分类号： H01L218234
CPC分类号： H01L27/08 , H01L27/0629
摘要： A method of fabricating high quality passive components having reduced capacitive and magnetic effects by using a Schottky diode underlying the passive components in the manufacture of integrated circuits is described. A Schottky diode is formed completely covering an active area where passive devices are to be formed. The Schottky diode is covered with a dielectric layer. Passive components are formed overlying the dielectric layer wherein the Schottky diode reduces substrate noise resulting in high quality of the passive components.
摘要翻译：描述了通过使用在集成电路的制造中的无源部件下面的肖特基二极管来制造具有降低的电容和磁效应的高质量无源部件的方法。肖特基二极管完全覆盖要形成无源器件的有源区域。肖特基二极管被绝缘层覆盖。无源元件形成在电介质层上方，其中肖特基二极管降低衬底噪声，导致无源元件的高质量。

2. 发明授权

US06730573B1 MIM and metal resistor formation at CU beol using only one extra mask 有权
标题翻译： MIM和金属电阻器形成在CU beol仅使用一个额外的掩模
公开(公告)号：US06730573B1
公开(公告)日：2004-05-04
申请号：US10286257
申请日：2002-11-01
申请人： Chit Hwei Ng , Chaw Sing Ho , Lup San Leong , Shao Kai , Raymond Jacob Joy , Sanford Chu , Sajan Marokkey Raphael
发明人： Chit Hwei Ng , Chaw Sing Ho , Lup San Leong , Shao Kai , Raymond Jacob Joy , Sanford Chu , Sajan Marokkey Raphael
IPC分类号： H01L2120
CPC分类号： H01L28/24 , H01L21/76838 , H01L23/5223 , H01L23/5228 , H01L23/5252 , H01L23/5329 , H01L27/0682 , H01L27/0805 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make
摘要翻译：已经开发了使用单镶嵌或双镶嵌加工制造同时高容量，小于0.13微米的金属 - 绝缘体 - 金属电容器，金属电阻器和金属互连的改进方法。关键的优点是同时使用一个额外的掩模掩模版同时形成MIM电容和电阻。克服了BEOL后端存在的几个当前的障碍，即：（a）使用两个或更多个光掩膜使<0.13μm的MIM电容器，（b）凹凸的铜表面，当电介质直接沉积时（c）当在底部MIM板层上尝试蚀刻停止时，（c）蚀刻期间的颗粒产生问题，最后，（d）在需要大的铜MIM板时发生CMP期间的凹陷，随后的电容匹配问题。该集成方法克服了上述障碍，同时使用镶嵌处理形成MIM电容器，金属电阻器和金属互连。此外，本文所述的形成MIM电容器的方法也可用于在现场可编程门阵列FPGA中形成反熔丝器件。

3. 发明授权

US06576526B2 Darc layer for MIM process integration 有权
标题翻译：用于MIM工艺集成的Darc层
公开(公告)号：US06576526B2
公开(公告)日：2003-06-10
申请号：US09900398
申请日：2001-07-09
申请人： Shao Kai , Wu-Guan Ping , Chen Liang , Cheng-Wei Hua , Sanford Chu , Daniel Yen
发明人： Shao Kai , Wu-Guan Ping , Chen Liang , Cheng-Wei Hua , Sanford Chu , Daniel Yen
IPC分类号： H01L2120
CPC分类号： H01L28/55 , H01L21/31122 , H01L21/32136
摘要： A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of Anti Reflective Coating. An etch is then performed to form the second electrode of the MIM capacitor (using the etch stop layer to stop this etch), MIM spacers are formed on the sidewalls of the second electrode of the MIM capacitor (also using the etch stop layer to stop this etch). The dielectric and first electrode of the MIM capacitor are formed by etching through the second layer of insulation and the first layer of metal. This is followed by conventional processing to create contact points to the MIM capacitor.
摘要翻译：为MIM电容器的创建提供了新的处理顺序。该过程开始于沉积第一层金属。接下来是沉积列表，薄层金属，一层绝缘层，第二层金属和一层抗反射涂层。然后进行蚀刻以形成MIM电容器的第二电极（使用蚀刻停止层来停止该蚀刻），MIM间隔物形成在MIM电容器的第二电极的侧壁上（也使用蚀刻停止层停止这个蚀刻）。 MIM电容器的电介质和第一电极通过蚀刻穿过第二绝缘层和第一金属层而形成。接下来是常规处理以产生与MIM电容器的接触点。

4. 发明授权

US06780727B2 Method for forming a MIM (metal-insulator-metal) capacitor 有权
标题翻译：用于形成MIM（金属 - 绝缘体 - 金属）电容器的方法
公开(公告)号：US06780727B2
公开(公告)日：2004-08-24
申请号：US10132244
申请日：2002-04-25
申请人： Ng Chit Hwei , Shao Kai , Bao Guang Wen , Tjoa Tjin Tjin , Sanford Chu
发明人： Ng Chit Hwei , Shao Kai , Bao Guang Wen , Tjoa Tjin Tjin , Sanford Chu
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/0276 , H01L21/32139 , H01L27/0805
摘要： Methods for forming a metal-insulator-metal (MIM) capacitor using an organic anti-reflective coating (ARC) are described. The first electrode of the MIM capacitor is formed from a first metal layer. The organic ARC is applied, and the second electrode of the MIM capacitor is formed from a second metal layer. The organic ARC is then removed using a nominal clean technique. Because the organic ARC is removed, the performance of the MIM capacitor is improved. Specifically, the breakdown voltage of the MIM capacitor increases and the leakage current decreases.
摘要翻译：描述了使用有机抗反射涂层（ARC）形成金属 - 绝缘体 - 金属（MIM）电容器的方法。 MIM电容器的第一电极由第一金属层形成。施加有机ARC，并且MIM电容器的第二电极由第二金属层形成。然后使用标称清洁技术除去有机ARC。由于去除了有机ARC，因此提高了MIM电容器的性能。具体地说，MIM电容器的击穿电压增加，漏电流减小。

5. 发明授权

US06746914B2 Metal sandwich structure for MIM capacitor onto dual damascene 有权
标题翻译：金属夹层结构MIM电容器到双镶嵌
公开(公告)号：US06746914B2
公开(公告)日：2004-06-08
申请号：US10140644
申请日：2002-05-07
申请人： Shao Kai , Ng Hwei , Sanford Chu
发明人： Shao Kai , Ng Hwei , Sanford Chu
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L21/76838 , H01L28/60
摘要： A first and second damascene copper interconnect plug are created over the surface of a substrate. A MIM capacitor, which is aligned with the second damascene copper interconnect plug, is created by a one-time etch of a stack of layers comprising Ta/capacitor dielectric/Ta. Copper interconnects are then created aligned with the MIM capacitor and the second damascene interconnect plug.
摘要翻译：在衬底的表面上形成第一和第二镶嵌铜互连插头。与第二镶嵌铜互连插塞对准的MIM电容器通过一次蚀刻包括Ta /电容器电介质/ Ta的层的叠层来产生。然后，与MIM电容器和第二镶嵌互连插头对准铜互连。

6. 发明授权

US06218234B1 Dual gate and double poly capacitor analog process integration 失效
标题翻译：双门和双电容模拟过程集成
公开(公告)号：US06218234B1
公开(公告)日：2001-04-17
申请号：US09298934
申请日：1999-04-26
申请人： Xing Yu , Shao Kai
发明人： Xing Yu , Shao Kai
IPC分类号： H01L218242
CPC分类号： H01L27/0629
摘要： A method for integrating the dual gate and double poly capacitor processes to fabricate an analog capacitor integrated circuit device is described. An isolation region is provided separating a first active area from a second active area in a semiconductor substrate. A first gate oxide layer is formed overlying the semiconductor substrate in both active areas. A first polysilicon layer is deposited overlying the first gate oxide layer and the isolation region. An capacitor dielectric layer comprising an oxide layer and a nitride layer is deposited overlying the first polysilicon layer. The capacitor dielectric layer and first polysilicon layer are etched away where they are not covered by a mask to form a first polysilicon gate electrode in the first area and a polysilicon capacitor bottom plate and overlying capacitor dielectric overlying the isolation region. The first gate oxide layer is removed in the second area and a thinner second gate oxide layer is formed in the second area. A second polysilicon layer is deposited overlying the second gate oxide layer, bottom capacitor plate and capacitor dielectric, and the first polysilicon gate electrode. The second polysilicon layer is etched away where it is not covered by a mask to form a second polysilicon gate electrode in the second area and to form a top capacitor plate overlying the bottom capacitor plate having the capacitor dielectric layer therebetween.
摘要翻译：描述了一种用于整合双栅极和双重多晶硅电容器工艺以制造模拟电容器集成电路器件的方法。提供了隔离区域，其将第一有源区域与半导体衬底中的第二有源区域分开。在两个有源区域中形成覆盖半导体衬底的第一栅极氧化物层。第一多晶硅层沉积在第一栅极氧化物层和隔离区上。包括氧化物层和氮化物层的电容器电介质层沉积在第一多晶硅层上。电容器电介质层和第一多晶硅层被蚀刻掉，其中它们不被掩模覆盖，以在第一区域中形成第一多晶硅栅电极，并且在多晶硅电容器底板和覆盖隔离区域的上覆电容器电介质上。在第二区域中去除第一栅极氧化物层，并且在第二区域中形成更薄的第二栅极氧化物层。沉积第二多晶硅层，覆盖第二栅极氧化物层，底部电容器板和电容器电介质，以及第一多晶硅栅电极。第二多晶硅层被蚀刻掉，其未被掩模覆盖，以在第二区域中形成第二多晶硅栅电极，并且形成覆盖在其间的电容器电介质层的底部电容器板的顶部电容器板。

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