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1. 发明授权

US07200772B2 Methods and apparatus to reinitiate failed processors in multiple-processor systems 有权
标题翻译：在多处理器系统中重新启动故障处理器的方法和设备
公开(公告)号：US07200772B2
公开(公告)日：2007-04-03
申请号：US10425805
申请日：2003-04-29
申请人： Sham Datta , Vincent Zimmer , Michael Rothman , Andy Miga
发明人： Sham Datta , Vincent Zimmer , Michael Rothman , Andy Miga
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/0757
摘要： Methods and apparatus to reinitiate failed processors in multiple-processor systems are described herein. In an example method, a failure associated with a first processor of a plurality of processors in a multiple-processor system is detected by a second processor of the plurality of processors. In response to detection of the failure associated with the first processor, the second processor restores the first processor.
摘要翻译：本文描述了在多处理器系统中重新启动故障处理器的方法和装置。在示例性方法中，与多处理器系统中的多个处理器的第一处理器相关联的故障由多个处理器的第二处理器检测。响应于检测到与第一处理器相关联的故障，第二处理器恢复第一处理器。

2. 发明申请

US20090172372A1 METHODS AND APPARATUS FOR GENERATING SYSTEM MANAGEMENT INTERRUPTS 有权
标题翻译：用于生成系统管理中断的方法和装置
公开(公告)号：US20090172372A1
公开(公告)日：2009-07-02
申请号：US11967299
申请日：2007-12-31
申请人： Mohan J. Kumar , Sarathy Jayakumar , Sham Datta
发明人： Mohan J. Kumar , Sarathy Jayakumar , Sham Datta
IPC分类号： G06F9/26
CPC分类号： G06F9/4812
摘要： A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed.
摘要翻译：一种方法包括确定多个存储器地址，每个存储器地址彼此不同。该方法还包括产生多个系统管理中断处理器中断，每个系统管理中断处理器中断在系统中的多个处理器中具有对应的处理器，并且每个系统管理中断处理器中断包括多个存储器地址之一。该方法还包括将每个系统管理中断处理器中断引导到相应的处理器。还公开了一种相关的机器可读介质。

3. 发明申请

US20080040524A1 System management mode using transactional memory 审中-公开
标题翻译：使用事务性存储器的系统管理模式
公开(公告)号：US20080040524A1
公开(公告)日：2008-02-14
申请号：US11503689
申请日：2006-08-14
申请人： Vincent J. Zimmer , Sham Datta , Michael A. Rothman
发明人： Vincent J. Zimmer , Sham Datta , Michael A. Rothman
IPC分类号： G06F13/24 , G06F13/32
CPC分类号： G06F13/24
摘要： Embodiments of a system and method for servicing a hidden execution mode event in a multiprocessor computer system is described. A plurality of event handlers and shared memory resources are loaded or stored in a transactional memory space that is accessible to a hidden execution mode supported by each of a plurality of processors in the multiprocessor system. The event handlers are dispatched to different processors among the plurality of processors in response to the hidden execution mode event. A resource locking mechanism comprising a linked-list mechanism that stores entries consisting of work items to be executed by the processors, enables a specified resource of the one or more shared resources to be accessed by only one event handler at a time. The hidden execution mode event comprises a System Management Mode of a microprocessor, and the hidden execution mode event can be either a System Management Interrupt event or a Processor Management Interrupt event. The transactional memory can be either Hardware Transactional Memory or Software Transactional Memory.
摘要翻译：描述了用于在多处理器计算机系统中处理隐藏执行模式事件的系统和方法的实施例。多个事件处理程序和共享存储器资源被加载或存储在可由多处理器系统中的多个处理器中的每一个支持的隐藏执行模式访问的事务存储器空间中。响应于隐藏的执行模式事件，将事件处理程序调度到多个处理器中的不同处理器。一种资源锁定机制，包括存储由待处理器执行的工作项组成的条目的链表机制，使一个或多个共享资源的指定资源一次只能由一个事件处理程序访问。隐藏执行模式事件包括微处理器的系统管理模式，隐藏执行模式事件可以是系统管理中断事件或处理器管理中断事件。事务内存可以是硬件事务内存或软件事务内存。

4. 发明授权

US06601166B1 Mechanism for booting a computer through a network 有权
标题翻译：通过网络引导计算机的机制
公开(公告)号：US06601166B1
公开(公告)日：2003-07-29
申请号：US09471792
申请日：1999-12-23
申请人： Mani Ayyar , Sham Datta , Andrew Fish
发明人： Mani Ayyar , Sham Datta , Andrew Fish
IPC分类号： G06F9445
CPC分类号： G06F9/4416
摘要： A mechanism is provided for booting a computer system that is capable of implementing different instruction set architectures, through a network. An embodiment of the invention includes a network controller implemented for a first ISA and a processor capable of implementing programs written in a second ISA as well as programs written in the first ISA. Following preliminary boot operations provided through non-volatile system memory, a network boot program provided by the network controller is implemented. The boot program requests the non-volatile system memory for an indication of the operating system to be loaded and generates a boot request for the indicated operating system. When the indicated operating system is written in the second ISA, the boot program loads the OS to a specified location in system memory and sends the processor into a mode suitable for executing the second ISA.
摘要翻译：提供了一种用于启动能够通过网络实现不同指令集架构的计算机系统的机制。本发明的实施例包括为第一ISA实现的网络控制器和能够实现在第二ISA中写入的程序的处理器以及写入第一ISA的程序。在通过非易失性系统存储器提供的初步引导操作之后，实现由网络控制器提供的网络引导程序。引导程序请求非易失性系统存储器以指示要加载的操作系统，并为指示的操作系统生成引导请求。当所指示的操作系统被写入第二ISA中时，引导程序将OS加载到系统存储器中的指定位置，并将处理器发送到适于执行第二ISA的模式。

5. 发明申请

US20070174587A1 Address space emulation 有权
标题翻译：地址空间仿真
公开(公告)号：US20070174587A1
公开(公告)日：2007-07-26
申请号：US11323465
申请日：2005-12-30
申请人： Sham Datta , Robert Greiner , Frank Binns , Keshavan Tiruvallur , Rajesh Parthasarathy , Madhavan Parthasarathy
发明人： Sham Datta , Robert Greiner , Frank Binns , Keshavan Tiruvallur , Rajesh Parthasarathy , Madhavan Parthasarathy
IPC分类号： G06F15/00
CPC分类号： G06F9/342 , G06F9/30174 , G06F12/0292 , G06F12/063 , G06F2212/206
摘要： Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.
摘要翻译：装置和系统以及方法和物品可以操作以检测与配置存储器地址和第一存储器地址位大小相关联的输入/输出访问操作。配置存储器地址和相关联的配置数据可以被组合成具有大于第一存储器地址位大小（例如，32位）的第二存储器地址位大小（例如，64位）的分组。该分组可以用于为尝试与外围组件互连（PCI）接口的外围设备以及已经集成到与处理器相同的封装中的类似的平台设备进行通信的传统操作系统建立兼容性。

6. 发明申请

US20090172806A1 SECURITY MANAGEMENT IN MULTI-NODE, MULTI-PROCESSOR PLATFORMS 有权
标题翻译：多节点，多处理器平台的安全管理
公开(公告)号：US20090172806A1
公开(公告)日：2009-07-02
申请号：US11968128
申请日：2007-12-31
申请人： Mahesh S. Natu , Sham Datta
发明人： Mahesh S. Natu , Sham Datta
IPC分类号： G06F7/04
CPC分类号： G06F21/85
摘要： Multi-node and multi-processor security management is described in this application. Data may be secured in a TPM of any one of a plurality of nodes, each node including one or more processors. The secured data may be protected using hardware hooks to prevent unauthorized access to the secured information. Security hierarchy may be put in place to protect certain memory addresses from access by requiring permission by VMM, OS, ACM or processor hardware. The presence of secured data may be communicated to each of the nodes to ensure that data is protected. Other embodiments are described.
摘要翻译：本节介绍了多节点和多处理器的安全管理。可以在多个节点中的任一个的TPM中确保数据，每个节点包括一个或多个处理器。可以使用硬件钩来保护安全数据，以防止未经授权的访问安全信息。可以通过要求VMM，OS，ACM或处理器硬件的许可来保护安全层次结构以保护某些存储器地址不被访问。可以将安全数据的存在传送到每个节点以确保数据被保护。描述其他实施例。

7. 发明申请

US20090172639A1 FIRMWARE INTEGRITY VERIFICATION 审中-公开
标题翻译：固件完整性验证
公开(公告)号：US20090172639A1
公开(公告)日：2009-07-02
申请号：US11965295
申请日：2007-12-27
申请人： Mahesh Natu , Sham Datta , Ernie Brickell
发明人： Mahesh Natu , Sham Datta , Ernie Brickell
IPC分类号： G06F9/44
CPC分类号： G06F21/57
摘要： In some embodiments, the integrity of firmware stored in a non-volatile memory is verified prior to initiation of a firmware reset vector. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，在启动固件复位向量之前验证存储在非易失性存储器中的固件的完整性。描述和要求保护其他实施例。

8. 发明授权

US5630147A System management shadow port 失效
标题翻译：系统管理影子端口
公开(公告)号：US5630147A
公开(公告)日：1997-05-13
申请号：US601697
申请日：1996-02-15
申请人： Sham Datta , Jayesh Joshi , James P. Kardach
发明人： Sham Datta , Jayesh Joshi , James P. Kardach
IPC分类号： G06F1/32 , G06F11/00
CPC分类号： G06F1/3253 , G06F1/3203 , Y02B60/1235
摘要： A device and method for transferring data, address and status information concerning a former I/O bus cycle before a system management interrupt is initiated. A plurality of system management shadow registers samples information from a system bus. Such information is obtained by a register accessing the plurality of system management shadow registers through a common shadow port.
摘要翻译：一种用于在系统管理中断启动之前传送有关前一个I / O总线周期的数据，地址和状态信息的设备和方法。多个系统管理影子寄存器从系统总线采样信息。这样的信息通过通过公共影子端口访问多个系统管理影子寄存器的寄存器获得。

9. 发明授权

US08301907B2 Supporting advanced RAS features in a secured computing system 有权
标题翻译：支持安全计算系统中的高级RAS功能
公开(公告)号：US08301907B2
公开(公告)日：2012-10-30
申请号：US11863563
申请日：2007-09-28
申请人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
发明人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
IPC分类号： G06F11/30
CPC分类号： G06F15/16
摘要： Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand.
摘要翻译：提供了在LaGrande Technology（LT）控制下启动可靠性，可用性和可维护性特性后，提供可靠性，可用性和可维护性功能的系统和方法，或者可比较的安全技术，而不会影响安全性。在一个实施例中，该方法包括将至少一个特定能力添加到处理器，以实现CPU热插拔，CPU迁移，CPU热去除和按需容量中的至少一个。

10. 发明授权

US08146150B2 Security management in multi-node, multi-processor platforms 有权
标题翻译：多节点，多处理器平台的安全管理
公开(公告)号：US08146150B2
公开(公告)日：2012-03-27
申请号：US11968128
申请日：2007-12-31
申请人： Mahesh S. Natu , Sham Datta
发明人： Mahesh S. Natu , Sham Datta
IPC分类号： G06F7/04
CPC分类号： G06F21/85
摘要： Multi-node and multi-processor security management is described in this application. Data may be secured in a TPM of any one of a plurality of nodes, each node including one or more processors. The secured data may be protected using hardware hooks to prevent unauthorized access to the secured information. Security hierarchy may be put in place to protect certain memory addresses from access by requiring permission by VMM, OS, ACM or processor hardware. The presence of secured data may be communicated to each of the nodes to ensure that data is protected. Other embodiments are described.
摘要翻译：本节介绍了多节点和多处理器的安全管理。可以在多个节点中的任一个的TPM中确保数据，每个节点包括一个或多个处理器。可以使用硬件钩来保护安全数据，以防止未经授权的访问安全信息。可以通过要求VMM，OS，ACM或处理器硬件的许可来保护安全层级以保护某些存储器地址免受访问。可以将安全数据的存在传送到每个节点以确保数据被保护。描述其他实施例。

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