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    • 9. 发明授权
    • Method and apparatus for exiting a deadlock condition
    • 退出死锁状态的方法和装置
    • US06567414B2
    • 2003-05-20
    • US09183051
    • 1998-10-30
    • Feng DengJames P. Kardach
    • Feng DengJames P. Kardach
    • H04L1228
    • G06F13/4036
    • A bridge for communicating between a first and a second bus includes a first interface unit, a second interface unit and a buffer unit. The first interface unit is adapted to be coupled to the first bus. The second interface unit is adapted to be coupled to the second bus. The buffer unit is coupled to the first and second interface units. The buffer unit is adapted to receive a posted transaction from one of the first and second interface units. The buffer unit includes a posting buffer and a discard timer. The posting buffer is adapted to store the posted transaction. The discard timer is adapted to generate a discard timer expired signal after a predetermined time interval that the posted transaction has resided in the posting buffer. A method for exiting from a potential deadlock situation includes posting a transaction, tracking the length of time the transaction has been posted, and discarding the transaction after a predetermined time interval that the transaction has been posted.
    • 用于在第一和第二总线之间通信的桥接器包括第一接口单元,第二接口单元和缓冲单元。 第一接口单元适于耦合到第一总线。 第二接口单元适于耦合到第二总线。 缓冲单元耦合到第一和第二接口单元。 缓冲器单元适于从第一和第二接口单元之一接收已发布的事务。 缓冲单元包括发布缓冲器和丢弃定时器。 发布缓冲区适用于存储已发布的事务。 丢弃定时器适于在发布的事务已经驻留在发布缓冲器中的预定时间间隔之后生成丢弃定时器过期信号。 从潜在的死锁情况退出的方法包括发布交易,跟踪交易已经发布的时间长度,以及在交易已经过帐的预定时间间隔之后丢弃交易。
    • 10. 发明授权
    • System, apparatus, and method for managing power in a computer system
    • 用于管理计算机系统中的电力的系统,装置和方法
    • US5692202A
    • 1997-11-25
    • US581164
    • 1995-12-29
    • James P. KardachChih-Hung ChungJason Ziller
    • James P. KardachChih-Hung ChungJason Ziller
    • G06F1/32
    • G06F1/3215G06F1/3237G06F1/3275Y02B60/1221Y02B60/1228
    • A computer system for monitoring the activity of a bus controller of a processor and responsive thereto for controlling the power consumption of a target controller such as a memory controller coupled to the bus controller. The computer system includes a bus, a processor having a bus controller coupled to the bus, and a bus activity monitor, coupled to the bus controller, generating a bus activity signal indicative of activity in the bus controller. The computer system also includes a target controller, coupled to the bus controller, for controlling the exchange of information between the processor and a target circuit. The target controller has an input for receiving a sequencing signal. The computer system additionally includes a power management circuit for controlling a power consumption of the target controller. The power management circuit has an input for receiving the bus activity signal and, an output for generating the sequencing signal in response to the bus activity signal.
    • 一种用于监视处理器的总线控制器的活动并响应于此来控制诸如连接到总线控制器的存储器控​​制器的目标控制器的功耗的计算机系统。 计算机系统包括总线,具有耦合到总线的总线控制器的处理器和耦合到总线控制器的总线活动监视器,生成指示总线控制器中的活动的总线活动信号。 计算机系统还包括耦合到总线控制器的目标控制器,用于控制处理器和目标电路之间的信息交换。 目标控制器具有用于接收排序信号的输入。 计算机系统还包括用于控制目标控制器的功耗的电源管理电路。 功率管理电路具有用于接收总线活动信号的输入端和用于响应于总线活动信号产生排序信号的输出。