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1. 发明授权

US08161331B2 Data training system and method thereof 有权
标题翻译：数据训练系统及其方法
公开(公告)号：US08161331B2
公开(公告)日：2012-04-17
申请号：US11987611
申请日：2007-12-03
申请人： Seung-jun Bae , Seong-jin Jang
发明人： Seung-jun Bae , Seong-jin Jang
IPC分类号： G06K5/04 , G11B20/20
CPC分类号： G11C7/1072 , G11C11/401 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： A data training system and method thereof are provided. The example data training system may include a memory controller transmitting a given data pattern to a memory device, the memory controller first determining whether an error is present within the transmitted data pattern based on at least one error detection code, the at least one error detection code based on at least one of the given data pattern and the transmitted data pattern and second determining a data delay time for reducing an amount of skew based on whether the first determining step determines an error to be present within the transmitted data pattern.
摘要翻译：提供了一种数据训练系统及其方法。示例性数据训练系统可以包括将给定数据模式发送到存储器设备的存储器控制器，存储器控制器首先基于至少一个错误检测码来确定发送的数据模式内是否存在错误，该至少一个错误检测基于给定数据模式和所发送的数据模式中的至少一个的代码，以及第二确定用于减少偏移量的数据延迟时间，基于第一确定步骤是否确定存在于所发送的数据模式中的错误。

2. 发明申请

US20080130986A1 Data training system and method thereof 有权
标题翻译：数据训练系统及其方法
公开(公告)号：US20080130986A1
公开(公告)日：2008-06-05
申请号：US11987611
申请日：2007-12-03
申请人： Seung-jun Bae , Seong-jin Jang
发明人： Seung-jun Bae , Seong-jin Jang
IPC分类号： G06K9/62
CPC分类号： G11C7/1072 , G11C11/401 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： A data training system and method thereof are provided. The example data training system may include a memory controller transmitting a given data pattern to a memory device, the memory controller first determining whether an error is present within the transmitted data pattern based on at least one error detection code, the at least one error detection code based on at least one of the given data pattern and the transmitted data pattern and second determining a data delay time for reducing an amount of skew based on whether the first determining step determines an error to be present within the transmitted data pattern.
摘要翻译：提供了一种数据训练系统及其方法。示例性数据训练系统可以包括将给定数据模式发送到存储器设备的存储器控制器，存储器控制器首先基于至少一个错误检测码来确定发送的数据模式内是否存在错误，该至少一个错误检测基于给定数据模式和所发送的数据模式中的至少一个的代码，以及第二确定用于减少偏移量的数据延迟时间，基于第一确定步骤是否确定存在于所发送的数据模式中的错误。

3. 发明申请

US20110309468A1 SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体芯片封装及其制造方法
公开(公告)号：US20110309468A1
公开(公告)日：2011-12-22
申请号：US13088442
申请日：2011-04-18
申请人： Tae-young Oh , Kwang-il Park , Seung-jun Bae , Yun-seok Yang , Young-soo Sohn , Si-hong Kim
发明人： Tae-young Oh , Kwang-il Park , Seung-jun Bae , Yun-seok Yang , Young-soo Sohn , Si-hong Kim
IPC分类号： H01L23/58 , H01L21/58
CPC分类号： H01L25/0657 , H01L24/16 , H01L24/94 , H01L25/50 , H01L2224/0557 , H01L2224/06131 , H01L2224/06135 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/30105 , H01L2224/05552
摘要： A semiconductor chip package includes a substrate, a first layer disposed on the substrate and a second layer substantially similar to and disposed on the first layer. The first layer has a first input/output (I/O) circuit, a first through-via connected to the first input/output (I/O) circuit and a second through-via that is not connected to the first I/O circuit. The second layer has a second I/O circuit, a third through-via connected to the second I/O circuit and a fourth through-via that is not connected to the second I/O circuit. The first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via. The package maybe fabricated by stacking the layers, and changing the orientation of the second layer relative to the first to ensure that the first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via.
摘要翻译：半导体芯片封装包括衬底，设置在衬底上的第一层和与第一层基本相似并且布置在第一层上的第二层。第一层具有第一输入/输出（I / O）电路，连接到第一输入/输出（I / O）电路的第一通孔和未连接到第一I / O的第二通孔电路。第二层具有第二I / O电路，连接到第二I / O电路的第三通孔和未连接到第二I / O电路的第四通孔。第一通孔连接到第四通孔，第二通孔连接到第三通孔。封装可以通过堆叠层制造，并且相对于第一层改变第二层的取向以确保第一通孔连接到第四通孔，而第二通孔连接到第三通孔 -通过。

4. 发明授权

US07868790B2 Single ended pseudo differential interconnection circuit and single ended pseudo differential signaling method 有权
标题翻译：单端伪差分互连电路和单端伪差分信号方法
公开(公告)号：US07868790B2
公开(公告)日：2011-01-11
申请号：US12453375
申请日：2009-05-08
申请人： Seung-jun Bae
发明人： Seung-jun Bae
IPC分类号： H03M5/00
CPC分类号： H03K5/2481 , G06F13/4072
摘要： A single ended pseudo differential signaling method may add a 1-bit signal to n-bit data if transmitting the n-bit data. Neighboring two signals among the 1-bit signal and data signals are compared to each other to generate detection signals.
摘要翻译：如果发送n位数据，则单端伪差分信令方法可以将1位信号添加到n位数据。将1比特信号和数据信号中的相邻两个信号相互比较以产生检测信号。

5. 发明申请

US20090219179A1 Single ended pseudo differential interconnection circuit and single ended pseudo differential signaling method 有权
标题翻译：单端伪差分互连电路和单端伪差分信号方法
公开(公告)号：US20090219179A1
公开(公告)日：2009-09-03
申请号：US12453375
申请日：2009-05-08
申请人： Seung-jun Bae
发明人： Seung-jun Bae
IPC分类号： H03M5/00
CPC分类号： H03K5/2481 , G06F13/4072
摘要： A single ended pseudo differential signaling method may add a 1-bit signal to n-bit data if transmitting the n-bit data. Neighboring two signals among the 1-bit signal and data signals are compared to each other to generate detection signals.
摘要翻译：如果发送n位数据，则单端伪差分信令方法可以将1位信号添加到n位数据。将1比特信号和数据信号中的相邻两个信号相互比较以产生检测信号。

6. 发明授权

US08390317B2 Bidirectional equalizer with CMOS inductive bias circuit 有权
标题翻译：带CMOS感应偏置电路的双向均衡器
公开(公告)号：US08390317B2
公开(公告)日：2013-03-05
申请号：US12832212
申请日：2010-07-08
申请人： Seung-jun Bae , Young-sik Kim , Sang-hyup Kwak
发明人： Seung-jun Bae , Young-sik Kim , Sang-hyup Kwak
IPC分类号： H03K19/0175
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1057 , G11C7/1084 , H03K19/018521
摘要： An integrated circuit (IC) device, system and related method of communicating data are described. The IC device includes; a data port configured to provide output data to a channel and receive input data from the channel, an impedance matching circuit connected to the data port and configured to operate as an output driver circuit when the output data is being transmitted and as an on die termination circuit when the input data is being received, and an active inductive bias circuit connected to the data port in parallel with the impedance matching circuit, and configured to adjust the impedance of the data port to the channel during transmission of the output data as a function of output data frequency and adjust the impedance of the data port to the channel during receipt of the input data as a function of input data frequency.
摘要翻译：描述了一种用于传送数据的集成电路（IC）装置，系统和相关方法。 IC器件包括：数据端口，被配置为向通道提供输出数据并从所述通道接收输入数据;阻抗匹配电路，连接到所述数据端口，并且被配置为当所述输出数据被发送时作为输出驱动器电路工作，并且作为管芯端接接收输入数据时的电路以及与阻抗匹配电路并联连接到数据端口的有源感应偏置电路，并且被配置为在输出数据作为功能的传输期间调整数据端口到通道的阻抗的输出数据频率，并根据输入数据频率调整输入数据接收期间数据端口到通道的阻抗。

7. 发明授权

US07814239B2 Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods 有权
标题翻译：实现时钟镜像方案和相关内存系统的内存设备和时钟镜像方法
公开(公告)号：US07814239B2
公开(公告)日：2010-10-12
申请号：US12045289
申请日：2008-03-10
申请人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
发明人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
IPC分类号： G06F3/00
CPC分类号： G11C5/063 , G06F1/10 , G11C7/1045 , G11C7/22 , G11C7/225 , G11C11/4076 , G11C2207/105
摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.
摘要翻译：存储器件被配置为在第一和第二数据输入/输出模式下操作。存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。时钟信号线被配置为将时钟传送到存储器件内部的集成电路。第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

8. 发明授权

US07772907B2 Linear digital phase interpolator and semi-digital delay locked loop (DLL) 有权
标题翻译：线性数字相位插值器和半数字延迟锁定环（DLL）
公开(公告)号：US07772907B2
公开(公告)日：2010-08-10
申请号：US12255170
申请日：2008-10-21
申请人： Jin-gook Kim , Seung-jun Bae , Kwang-il Park
发明人： Jin-gook Kim , Seung-jun Bae , Kwang-il Park
IPC分类号： H03H3/00 , H03K5/13
CPC分类号： H03L7/0814 , H03L7/07
摘要： Provided are a digital phase interpolator, which performs linear phase interpolation irrelevantly to input order of two input signals, and a semi-digital delay locked loop (DLL), which includes and controls the same. The phase interpolator includes: a first clocked inverter controlled by a phase indicating signal and providing a first output signal to a common output terminal by inverting a first input signal, and a second clocked inverter controlled by the phase indicating signal and providing a second output signal to the common output terminal by inverting the second input signal. The second clocked inverter is clocked by the first input signal when the phase indicating signal is in a first logic state, and the first clocked inverter is clocked by the second input signal when the phase indicating signal is in a second logic state. The phase indicating signal indicates a lead/lag phase relationship between the first and second input signals and is generated in a controller of a circuit of the semi-digital DLL.
摘要翻译：提供了一种数字相位内插器，其执行与两个输入信号的输入顺序无关的线性相位插值和包括并控制相同的半数字延迟锁定环（DLL）。相位插值器包括：由相位指示信号控制的第一时钟反相器，并通过反相第一输入信号向公共输出端提供第一输出信号;以及由相位指示信号控制的第二时钟反相器，并提供第二输出信号通过反转第二输入信号到公共输出端子。当相位指示信号处于第一逻辑状态时，第二时钟反相器由第一输入信号计时，当相位指示信号处于第二逻辑状态时，第一时钟反相器由第二输入信号计时。相位指示信号表示第一和第二输入信号之间的引导/滞后相位关系，并且在半数字DLL的电路的控制器中产生。

9. 发明申请

US20100045491A1 INPUT/OUTPUT (IO) INTERFACE AND METHOD OF TRANSMITTING IO DATA 失效
标题翻译：输入/输出（IO）接口和传输IO数据的方法
公开(公告)号：US20100045491A1
公开(公告)日：2010-02-25
申请号：US12547204
申请日：2009-08-25
申请人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
发明人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
IPC分类号： H03M7/00
CPC分类号： H03M5/06 , G11C7/1006
摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.
摘要翻译：输入/输出（IO）接口包括数据编码器，其对具有不同定时的多个并行数据中的每一个进行编码并生成多个编码数据;以及交流（AC）耦合传输单元，其传输多个的交流耦合方法中的编码数据。数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

10. 发明授权

US09059698B2 Integrated circuit devices using power supply circuits with feedback from a replica load 有权
标题翻译：使用具有来自复制负载的反馈的电源电路的集成电路器件
公开(公告)号：US09059698B2
公开(公告)日：2015-06-16
申请号：US13240635
申请日：2011-09-22
申请人： Su-yeon Doo , Seung-jun Bae , Kwang-il Park , Young-soo Sohn
发明人： Su-yeon Doo , Seung-jun Bae , Kwang-il Park , Young-soo Sohn
IPC分类号： G05F1/00 , H03K19/003 , G05F1/575
CPC分类号： H03K19/00361 , G05F1/575
摘要： An integrated circuit device includes an external power supply input configured to be coupled to an external power supply and a digital circuit, such as a clock signal generator circuit, that generates noise at a power supply input thereof. The device further includes a replica load circuit and a power supply circuit coupled to the external power supply input, to a power supply input of the digital circuit and to a power supply input of the replica load circuit. The power supply circuit is configured to selectively couple the external power supply node to the power supply input of the digital circuit responsive to a voltage at the power supply input of the replica load circuit. The replica load circuit may be configured to provide a load that varies responsive to a voltage at the power supply input of the digital circuit.
摘要翻译：集成电路装置包括被配置为耦合到外部电源的外部电源输入和在其电源输入处产生噪声的数字电路，例如时钟信号发生器电路。该装置还包括复制负载电路和耦合到外部电源输入的电源电路，数字电路的电源输入和复制负载电路的电源输入。电源电路被配置为响应于复制负载电路的电源输入处的电压来选择性地将外部电源节点耦合到数字电路的电源输入。复制负载电路可以被配置为提供响应于数字电路的电源输入处的电压而变化的负载。

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