专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07814239B2 Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods 有权
标题翻译：实现时钟镜像方案和相关内存系统的内存设备和时钟镜像方法
公开(公告)号：US07814239B2
公开(公告)日：2010-10-12
申请号：US12045289
申请日：2008-03-10
申请人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
发明人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
IPC分类号： G06F3/00
CPC分类号： G11C5/063 , G06F1/10 , G11C7/1045 , G11C7/22 , G11C7/225 , G11C11/4076 , G11C2207/105
摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.
摘要翻译：存储器件被配置为在第一和第二数据输入/输出模式下操作。存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。时钟信号线被配置为将时钟传送到存储器件内部的集成电路。第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

2. 发明授权

US07772907B2 Linear digital phase interpolator and semi-digital delay locked loop (DLL) 有权
标题翻译：线性数字相位插值器和半数字延迟锁定环（DLL）
公开(公告)号：US07772907B2
公开(公告)日：2010-08-10
申请号：US12255170
申请日：2008-10-21
申请人： Jin-gook Kim , Seung-jun Bae , Kwang-il Park
发明人： Jin-gook Kim , Seung-jun Bae , Kwang-il Park
IPC分类号： H03H3/00 , H03K5/13
CPC分类号： H03L7/0814 , H03L7/07
摘要： Provided are a digital phase interpolator, which performs linear phase interpolation irrelevantly to input order of two input signals, and a semi-digital delay locked loop (DLL), which includes and controls the same. The phase interpolator includes: a first clocked inverter controlled by a phase indicating signal and providing a first output signal to a common output terminal by inverting a first input signal, and a second clocked inverter controlled by the phase indicating signal and providing a second output signal to the common output terminal by inverting the second input signal. The second clocked inverter is clocked by the first input signal when the phase indicating signal is in a first logic state, and the first clocked inverter is clocked by the second input signal when the phase indicating signal is in a second logic state. The phase indicating signal indicates a lead/lag phase relationship between the first and second input signals and is generated in a controller of a circuit of the semi-digital DLL.
摘要翻译：提供了一种数字相位内插器，其执行与两个输入信号的输入顺序无关的线性相位插值和包括并控制相同的半数字延迟锁定环（DLL）。相位插值器包括：由相位指示信号控制的第一时钟反相器，并通过反相第一输入信号向公共输出端提供第一输出信号;以及由相位指示信号控制的第二时钟反相器，并提供第二输出信号通过反转第二输入信号到公共输出端子。当相位指示信号处于第一逻辑状态时，第二时钟反相器由第一输入信号计时，当相位指示信号处于第二逻辑状态时，第一时钟反相器由第二输入信号计时。相位指示信号表示第一和第二输入信号之间的引导/滞后相位关系，并且在半数字DLL的电路的控制器中产生。

3. 发明授权

US08180939B2 Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods 有权
公开(公告)号：US08180939B2
公开(公告)日：2012-05-15
申请号：US13013157
申请日：2011-01-25
申请人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
发明人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
IPC分类号： G06F13/12
CPC分类号： G11C5/063 , G06F1/10 , G11C7/1045 , G11C7/22 , G11C7/225 , G11C11/4076 , G11C2207/105
摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

4. 发明申请

US20110029697A1 MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS 有权
标题翻译：存储器件实现时钟模式和相关的存储器系统和时钟模式
公开(公告)号：US20110029697A1
公开(公告)日：2011-02-03
申请号：US12902328
申请日：2010-10-12
申请人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
发明人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
IPC分类号： G06F3/00
CPC分类号： G11C5/063 , G06F1/10 , G11C7/1045 , G11C7/22 , G11C7/225 , G11C11/4076 , G11C2207/105
摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.
摘要翻译：存储器件被配置为在第一和第二数据输入/输出模式下操作。存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。时钟信号线被配置为将时钟传送到存储器件内部的集成电路。第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

5. 发明申请

US20080225623A1 MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS 有权
标题翻译：存储器件实现时钟模式和相关的存储器系统和时钟模式
公开(公告)号：US20080225623A1
公开(公告)日：2008-09-18
申请号：US12045289
申请日：2008-03-10
申请人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
发明人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
IPC分类号： G11C8/00
CPC分类号： G11C5/063 , G06F1/10 , G11C7/1045 , G11C7/22 , G11C7/225 , G11C11/4076 , G11C2207/105
摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.
摘要翻译：存储器件被配置为在第一和第二数据输入/输出模式下操作。存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。时钟信号线被配置为将时钟传送到存储器件内部的集成电路。第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

6. 发明申请

US20110185219A1 MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS 有权
公开(公告)号：US20110185219A1
公开(公告)日：2011-07-28
申请号：US13013157
申请日：2011-01-25
申请人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
发明人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
IPC分类号： G06F1/08
CPC分类号： G11C5/063 , G06F1/10 , G11C7/1045 , G11C7/22 , G11C7/225 , G11C11/4076 , G11C2207/105
摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

7. 发明授权

US08151010B2 Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods 有权
标题翻译：实现时钟镜像方案和相关内存系统的内存设备和时钟镜像方法
公开(公告)号：US08151010B2
公开(公告)日：2012-04-03
申请号：US12902328
申请日：2010-10-12
申请人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
发明人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
IPC分类号： G06F3/00
CPC分类号： G11C5/063 , G06F1/10 , G11C7/1045 , G11C7/22 , G11C7/225 , G11C11/4076 , G11C2207/105
摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.
摘要翻译：存储器件被配置为在第一和第二数据输入/输出模式下操作。存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。时钟信号线被配置为将时钟传送到存储器件内部的集成电路。第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

8. 发明申请

US20100045491A1 INPUT/OUTPUT (IO) INTERFACE AND METHOD OF TRANSMITTING IO DATA 失效
标题翻译：输入/输出（IO）接口和传输IO数据的方法
公开(公告)号：US20100045491A1
公开(公告)日：2010-02-25
申请号：US12547204
申请日：2009-08-25
申请人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
发明人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
IPC分类号： H03M7/00
CPC分类号： H03M5/06 , G11C7/1006
摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.
摘要翻译：输入/输出（IO）接口包括数据编码器，其对具有不同定时的多个并行数据中的每一个进行编码并生成多个编码数据;以及交流（AC）耦合传输单元，其传输多个的交流耦合方法中的编码数据。数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

9. 发明申请

US20110309468A1 SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体芯片封装及其制造方法
公开(公告)号：US20110309468A1
公开(公告)日：2011-12-22
申请号：US13088442
申请日：2011-04-18
申请人： Tae-young Oh , Kwang-il Park , Seung-jun Bae , Yun-seok Yang , Young-soo Sohn , Si-hong Kim
发明人： Tae-young Oh , Kwang-il Park , Seung-jun Bae , Yun-seok Yang , Young-soo Sohn , Si-hong Kim
IPC分类号： H01L23/58 , H01L21/58
CPC分类号： H01L25/0657 , H01L24/16 , H01L24/94 , H01L25/50 , H01L2224/0557 , H01L2224/06131 , H01L2224/06135 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/30105 , H01L2224/05552
摘要： A semiconductor chip package includes a substrate, a first layer disposed on the substrate and a second layer substantially similar to and disposed on the first layer. The first layer has a first input/output (I/O) circuit, a first through-via connected to the first input/output (I/O) circuit and a second through-via that is not connected to the first I/O circuit. The second layer has a second I/O circuit, a third through-via connected to the second I/O circuit and a fourth through-via that is not connected to the second I/O circuit. The first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via. The package maybe fabricated by stacking the layers, and changing the orientation of the second layer relative to the first to ensure that the first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via.
摘要翻译：半导体芯片封装包括衬底，设置在衬底上的第一层和与第一层基本相似并且布置在第一层上的第二层。第一层具有第一输入/输出（I / O）电路，连接到第一输入/输出（I / O）电路的第一通孔和未连接到第一I / O的第二通孔电路。第二层具有第二I / O电路，连接到第二I / O电路的第三通孔和未连接到第二I / O电路的第四通孔。第一通孔连接到第四通孔，第二通孔连接到第三通孔。封装可以通过堆叠层制造，并且相对于第一层改变第二层的取向以确保第一通孔连接到第四通孔，而第二通孔连接到第三通孔 -通过。

10. 发明申请

US20110292742A1 Stacked Semiconductor Memory Device, Memory System Including The Same, And Method Of Repairing Defects Of Through Silicon Vias 有权
标题翻译：堆叠的半导体存储器件，包括其的存储器系统以及修复通孔硅缺陷的方法
公开(公告)号：US20110292742A1
公开(公告)日：2011-12-01
申请号：US13085776
申请日：2011-04-13
申请人： Tae-Young Oh , Kwang-il Park , Yun-Seok Yang , Young-Soo Sohn , Si-Hong Kim , Seung-Jun Bae
发明人： Tae-Young Oh , Kwang-il Park , Yun-Seok Yang , Young-Soo Sohn , Si-Hong Kim , Seung-Jun Bae
IPC分类号： G11C7/10 , H01L23/48
CPC分类号： G11C29/702 , G11C7/10 , H01L22/22 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06541
摘要： A stacked semiconductor memory device according to the inventive concepts may include a plurality of memory chips stacked above a processor chip, a plurality of TSVs, and I/O buffers. The TSVs may pass through the memory chips and are connected to the processor chip. I/O buffers may be coupled between all or part of the memory chips and the TSVs and may be selectively activated on the basis of defective states of the TSVs.
摘要翻译：根据本发明构思的叠层半导体存储器件可以包括堆叠在处理器芯片上方的多个存储器芯片，多个TSV和I / O缓冲器。 TSV可以通过存储器芯片并且连接到处理器芯片。 I / O缓冲器可以耦合在所有或部分存储器芯片和TSV之间，并且可以基于TSV的故障状态来选择性地激活。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式