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1. 发明申请

US20080182383A1 Method of removing an oxide and method of filling a trench using the same 有权
标题翻译：去除氧化物的方法和使用该方法填充沟槽的方法
公开(公告)号：US20080182383A1
公开(公告)日：2008-07-31
申请号：US12007640
申请日：2008-01-14
申请人： Seung-Heon Lee , Kyu-Tae Na , Ju-Wan Kim , Taek-Jung Kim
发明人： Seung-Heon Lee , Kyu-Tae Na , Ju-Wan Kim , Taek-Jung Kim
IPC分类号： H01L21/3065 , H01L21/762
CPC分类号： H01L21/31612 , H01L21/02164 , H01L21/02271 , H01L21/02337
摘要： A method of removing a portion of an oxide layer includes forming first byproducts by reacting a reaction gas with the oxide layer, the reaction gas including fluorine and nitrogen, reacting the reaction gas with the first byproducts to form second byproducts, and removing the second byproducts.
摘要翻译：除去一部分氧化物层的方法包括通过使反应气体与氧化物层反应形成第一副产物，反应气体包括氟和氮，使反应气体与第一副产物反应形成第二副产物，并除去第二副产物。

2. 发明授权

US07745305B2 Method of removing an oxide and method of filling a trench using the same 有权
标题翻译：去除氧化物的方法和使用该方法填充沟槽的方法
公开(公告)号：US07745305B2
公开(公告)日：2010-06-29
申请号：US12007640
申请日：2008-01-14
申请人： Seung-Heon Lee , Kyu-Tae Na , Ju-Wan Kim , Taek-Jung Kim
发明人： Seung-Heon Lee , Kyu-Tae Na , Ju-Wan Kim , Taek-Jung Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/31612 , H01L21/02164 , H01L21/02271 , H01L21/02337
摘要： A method of removing a portion of an oxide layer includes forming first byproducts by reacting a reaction gas with the oxide layer, the reaction gas including fluorine and nitrogen, reacting the reaction gas with the first byproducts to form second byproducts, and removing the second byproducts.
摘要翻译：除去一部分氧化物层的方法包括通过使反应气体与氧化物层反应形成第一副产物，反应气体包括氟和氮，使反应气体与第一副产物反应形成第二副产物，并除去第二副产物。

3. 发明授权

US07256091B2 Method of manufacturing a semiconductor device with a self-aligned polysilicon electrode 失效
标题翻译：制造具有自对准多晶硅电极的半导体器件的方法
公开(公告)号：US07256091B2
公开(公告)日：2007-08-14
申请号：US11149702
申请日：2005-06-09
申请人： Taek-Jung Kim , Min Kim
发明人： Taek-Jung Kim , Min Kim
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763 , H01L21/302
CPC分类号： H01L27/11521 , H01L21/76224 , H01L21/763 , H01L27/115
摘要： In a method of manufacturing a semiconductor device, an isolation pattern is formed on a substrate. The isolation pattern includes an opening that exposes a portion of the substrate. A preliminary polysilicon layer is formed on the substrate and the isolation pattern to partially fill up the opening. A sacrificial layer is formed on the preliminary polysilicon layer. The sacrificial layer is partially etched to expose a portion of the preliminary polysilicon layer formed on a shoulder portion of the isolation pattern. A first polysilicon layer is formed by etching the exposed portion of the preliminary polysilicon layer to enlarge an upper width of the opening. After the etched sacrificial layer is removed, a second polysilicon layer is formed on the first polysilicon layer to fill up the enlarged opening. Because the upper width of the opening is larger than the lower width, no seam or void would be generated in the second polysilicon layer, therefore improving the electrical characteristics and reliability of the device.
摘要翻译：在制造半导体器件的方法中，在衬底上形成隔离图案。隔离图案包括露出基板的一部分的开口。在基板和隔离图案上形成初步多晶硅层以部分地填充开口。在初步多晶硅层上形成牺牲层。牺牲层被部分蚀刻以暴露形成在隔离图案的肩部上的初步多晶硅层的一部分。通过蚀刻初步多晶硅层的暴露部分以扩大开口的上部宽度来形成第一多晶硅层。在去除蚀刻的牺牲层之后，在第一多晶硅层上形成第二多晶硅层以填满扩大的开口。因为开口的上部宽度大于下部宽度，所以在第二多晶硅层中不会产生接缝或空隙，从而改善了器件的电气特性和可靠性。

4. 发明申请

US20070004107A1 METHODS FOR FABRICATING INTEGRATED CIRCUIT FIELD EFFECT TRANSISTORS INCLUDING CHANNEL-CONTAINING FIN HAVING REGIONS OF HIGH AND LOW DOPING CONCENTRATIONS 有权
标题翻译：用于制造集成电路场效应晶体管的方法，包括具有高浓度和低掺杂浓度区域的通道含金属
公开(公告)号：US20070004107A1
公开(公告)日：2007-01-04
申请号：US11530651
申请日：2006-09-11
申请人： Deok-Hyung Lee , Byeong-Chan Lee , Si-Young Choi , Taek-Jung Kim , Yong-Hoon Son , In-Soo Jung
发明人： Deok-Hyung Lee , Byeong-Chan Lee , Si-Young Choi , Taek-Jung Kim , Yong-Hoon Son , In-Soo Jung
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823437 , H01L29/66803
摘要： Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit substrate. A channel region is provided in the fin that is doped a conductivity type and has a higher doping concentration of the conductivity type adjacent the top than remote from the top. A source region and a drain region are provided in the fin on opposite sides of the channel region, and an insulated gate electrode extends across the fin adjacent the channel region. Related fabrication methods also are described
摘要翻译：集成电路场效应晶体管包括集成电路基板和远离集成电路基板突出的翅片，沿着集成电路基板延伸，并且包括远离集成电路基板的顶部。沟道区域设置在散热片中，其掺杂有导电类型，并且具有比远离顶部更靠近顶部的导电类型的较高的掺杂浓度。源极区域和漏极区域设置在沟道区域的相对侧上的鳍片中，并且绝缘栅极电极在与沟道区域相邻的鳍片上延伸。还描述了相关的制造方法

5. 发明授权

US07521301B2 Methods for fabricating integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations 有权
标题翻译：制造集成电路场效应晶体管的方法，其包括具有高掺杂浓度和低掺杂浓度区域的含通道翅片
公开(公告)号：US07521301B2
公开(公告)日：2009-04-21
申请号：US11530651
申请日：2006-09-11
申请人： Deok-Hyung Lee , Byeong-Chan Lee , Si-Young Choi , Taek-Jung Kim , Yong-Hoon Son , In-Soo Jung
发明人： Deok-Hyung Lee , Byeong-Chan Lee , Si-Young Choi , Taek-Jung Kim , Yong-Hoon Son , In-Soo Jung
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823437 , H01L29/66803
摘要： Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit substrate. A channel region is provided in the fin that is doped a conductivity type and has a higher doping concentration of the conductivity type adjacent the top than remote from the top. A source region and a drain region are provided in the fin on opposite sides of the channel region, and an insulated gate electrode extends across the fin adjacent the channel region. Related fabrication methods also are described.
摘要翻译：集成电路场效应晶体管包括集成电路基板和远离集成电路基板突出的翅片，沿着集成电路基板延伸，并且包括远离集成电路基板的顶部。沟道区域设置在散热片中，其掺杂有导电类型，并且具有比远离顶部更靠近顶部的导电类型的较高的掺杂浓度。源极区域和漏极区域设置在沟道区域的相对侧上的鳍片中，并且绝缘栅极电极在与沟道区域相邻的鳍片上延伸。还描述了相关的制造方法。

6. 发明授权

US07122871B2 Integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations 有权
标题翻译：集成电路场效应晶体管，其包括具有高掺杂浓度和低掺杂浓度区域的含通道翅片
公开(公告)号：US07122871B2
公开(公告)日：2006-10-17
申请号：US10801614
申请日：2004-03-16
申请人： Deok-Hyung Lee , Byeong-Chan Lee , Si-Young Choi , Taek-Jung Kim , Yong-Hoon Son , In-Soo Jung
发明人： Deok-Hyung Lee , Byeong-Chan Lee , Si-Young Choi , Taek-Jung Kim , Yong-Hoon Son , In-Soo Jung
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823437 , H01L29/66803
摘要： Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit substrate. A channel region is provided in the fin that is doped a conductivity type and has a higher doping concentration of the conductivity type adjacent the top than remote from the top. A source region and a drain region are provided in the fin on opposite sides of the channel region, and an insulated gate electrode extends across the fin adjacent the channel region. Related fabrication methods also are described.
摘要翻译：集成电路场效应晶体管包括集成电路基板和远离集成电路基板突出的翅片，沿着集成电路基板延伸，并且包括远离集成电路基板的顶部。沟道区域设置在散热片中，其掺杂有导电类型，并且具有比远离顶部更靠近顶部的导电类型的较高的掺杂浓度。源极区域和漏极区域设置在沟道区域的相对侧上的鳍片中，并且绝缘栅极电极在与沟道区域相邻的鳍片上延伸。还描述了相关的制造方法。

7. 发明申请

US20050287763A1 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20050287763A1
公开(公告)日：2005-12-29
申请号：US11149702
申请日：2005-06-09
申请人： Taek-Jung Kim , Min Kim
发明人： Taek-Jung Kim , Min Kim
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763 , H01L21/8238 , H01L21/8247 , H01L27/115 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11521 , H01L21/76224 , H01L21/763 , H01L27/115
摘要： In a method of manufacturing a semiconductor device, an isolation pattern is formed on a substrate. The isolation pattern includes an opening that exposes a portion of the substrate. A preliminary polysilicon layer is formed on the substrate and the isolation pattern to partially fill up the opening. A sacrificial layer is formed on the preliminary polysilicon layer. The sacrificial layer is partially etched to expose a portion of the preliminary polysilicon layer formed on a shoulder portion of the isolation pattern. A first polysilicon layer is formed by etching the exposed portion of the preliminary polysilicon layer to enlarge an upper width of the opening. After the etched sacrificial layer is removed, a second polysilicon layer is formed on the first polysilicon layer to fill up the enlarged opening. Because the upper width of the opening is larger than the lower width, no seam or void would be generated in the second polysilicon layer, therefore improving the electrical characteristics and reliability of the device.
摘要翻译：在制造半导体器件的方法中，在衬底上形成隔离图案。隔离图案包括露出基板的一部分的开口。在基板和隔离图案上形成初步多晶硅层以部分地填充开口。在初步多晶硅层上形成牺牲层。牺牲层被部分蚀刻以暴露形成在隔离图案的肩部上的初步多晶硅层的一部分。通过蚀刻初步多晶硅层的暴露部分以扩大开口的上部宽度来形成第一多晶硅层。在去除蚀刻的牺牲层之后，在第一多晶硅层上形成第二多晶硅层以填满扩大的开口。因为开口的上部宽度大于下部宽度，所以在第二多晶硅层中不会产生接缝或空隙，从而改善了器件的电气特性和可靠性。

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