会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 10. 发明授权
    • Method for fabricating a high-voltage high-power integrated circuit device
    • 高压大功率集成电路器件的制造方法
    • US06855581B2
    • 2005-02-15
    • US10153975
    • 2002-05-23
    • Tae Moon RohDae Woo LeeYil Suk YangIl Yong ParkSang Gi KimJin Gun KooJong Dae Kim
    • Tae Moon RohDae Woo LeeYil Suk YangIl Yong ParkSang Gi KimJin Gun KooJong Dae Kim
    • H01L21/76H01L21/84H01L27/12
    • H01L27/1203H01L21/84
    • The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.
    • 本发明涉及使用其中绝缘膜和硅层依次层叠在硅衬底上的SOI结构的衬底的高压大功率集成电路器件的制造方法。 该方法包括以下步骤:在硅层上依次形成氧化物膜和光致抗蚀剂膜,然后使用沟槽掩模进行光刻工艺以对光刻胶膜进行图案化; 使用图案化的光致抗蚀剂膜作为掩模来图案化氧化膜,然后在图案化之后除去光致抗蚀剂膜; 使用所述图案化氧化膜作为掩模蚀刻所述硅层,直到所述绝缘膜暴露以形成沟槽; 在包括沟槽的整个表面上形成氮化物膜,执行退火处理并在整个表面上沉积多晶硅,使得沟槽被埋置; 并且顺序地去除多晶硅和氮化物膜,直到硅层暴露以使表面变平,从而形成用于在沟槽内的器件之间进行电隔离的器件隔离膜。 因此,本发明能够有效地降低高压大功率器件与逻辑CMOS器件之间的沟槽的隔离面积,能够容易地控制深井的浓度。