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1. 发明授权

US09875788B2 Low-power 5T SRAM with improved stability and reduced bitcell size 有权
公开(公告)号：US09875788B2
公开(公告)日：2018-01-23
申请号：US12731668
申请日：2010-03-25
申请人： Seong-Ook Jung , Hyunkook Park , Seung-Chul Song , Mohamed Hassan Abu-Rahma , Lixin Ge , Zhongze Wang , Beom-Mo Han
发明人： Seong-Ook Jung , Hyunkook Park , Seung-Chul Song , Mohamed Hassan Abu-Rahma , Lixin Ge , Zhongze Wang , Beom-Mo Han
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.

2. 发明申请

US20110235406A1 Low-Power 5T SRAM with Improved Stability and Reduced Bitcell Size 有权
标题翻译：低功耗5T SRAM，具有改进的稳定性和降低位单元大小
公开(公告)号：US20110235406A1
公开(公告)日：2011-09-29
申请号：US12731668
申请日：2010-03-25
申请人： Seong-Ook Jung , Hyunkook Park , Seung-Chul Song , Mohamed Hassan Abu-Rahma , Lixin Ge , Zhongze Wang , Beom-Mo Han
发明人： Seong-Ook Jung , Hyunkook Park , Seung-Chul Song , Mohamed Hassan Abu-Rahma , Lixin Ge , Zhongze Wang , Beom-Mo Han
IPC分类号： G11C11/00 , G11C8/08 , G11C7/00
CPC分类号： G11C11/412
摘要： A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.
摘要翻译： 5晶体管静态随机存取存储器（5T SRAM）设计用于减小电池尺寸和对工艺变化的抗扰性。 5T SRAM包括用于存储数据的存储元件，其中存储元件耦合到第一电压和接地电压。存储元件可以包括对称尺寸的交叉耦合的反相器。单个存取晶体管控制对存储元件的读取和写入操作。控制逻辑被配置为产生与读取操作的第一电压的值不同的写入操作的第一电压的值。

3. 发明授权

US09865330B2 Stable SRAM bitcell design utilizing independent gate FinFET 有权
公开(公告)号：US09865330B2
公开(公告)日：2018-01-09
申请号：US12939260
申请日：2010-11-04
申请人： Seong-Ook Jung , Mingu Kang , Hyunkook Park , Seung-Chul Song , Mohamed Abu-Rahma , Beom-Mo Han , Lixin Ge , Zhongze Wang
发明人： Seong-Ook Jung , Mingu Kang , Hyunkook Park , Seung-Chul Song , Mohamed Abu-Rahma , Beom-Mo Han , Lixin Ge , Zhongze Wang
IPC分类号： G11C11/412 , H01L27/11
CPC分类号： G11C11/4125 , H01L27/1104 , Y10T29/49117
摘要： Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.

4. 发明申请

US20120113708A1 Stable SRAM Bitcell Design Utilizing Independent Gate Finfet 有权
标题翻译：稳定的SRAM位单元设计采用独立的门极Finfet
公开(公告)号：US20120113708A1
公开(公告)日：2012-05-10
申请号：US12939260
申请日：2010-11-04
申请人： Seong-Ook Jung , Mingu Kang , Hyunkook Park , Seung-Chul Song , Mohamed Abu-Rahma , Beom-Mo Han , Lixin Ge , Zhongze Wang
发明人： Seong-Ook Jung , Mingu Kang , Hyunkook Park , Seung-Chul Song , Mohamed Abu-Rahma , Beom-Mo Han , Lixin Ge , Zhongze Wang
IPC分类号： G11C11/00 , H01R43/00
CPC分类号： G11C11/4125 , H01L27/1104 , Y10T29/49117
摘要： Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.
摘要翻译：利用独立栅极FinFET架构的稳定SRAM单元提供了诸如读静态噪声余量（RSNM）和写噪声余量（WNM）的器件参数中的常规SRAM单元的改进。示例性SRAM单元包括一对存储节点，一对位线，一对上拉器件，一对下拉器件和一对通栅器件。第一控制信号和第二控制信号被配置为调整传递门装置的驱动强度，并且第三控制信号被配置为调节上拉装置的驱动强度，其中第一控制信号被正交地传送到位线方向，并且第二和第三控制信号沿与位线方向相同的方向路由。通过在读写操作期间调整上拉和通过栅极器件的驱动强度，RSNM和WNM得到了改进。

5. 发明授权

US07872930B2 Testing a memory device having field effect transistors subject to threshold voltage shifts caused by bias temperature instability 有权
标题翻译：测试具有由偏置温度不稳定性引起的阈值电压偏移的场效应晶体管的存储器件
公开(公告)号：US07872930B2
公开(公告)日：2011-01-18
申请号：US12121560
申请日：2008-05-15
申请人： Nan Chen , Sian-Yee Sean Lee , Seong-Ook Jung , Zhongze Wang
发明人： Nan Chen , Sian-Yee Sean Lee , Seong-Ook Jung , Zhongze Wang
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/10 , G11C29/12005
摘要： A supply voltage is set for a memory device at a first supply voltage level. Test data is written to the memory device at the first supply voltage level in response to setting the supply voltage. The supply voltage is decreased for the memory device to a second supply voltage level below the first supply voltage level in response to writing the test data. The test data is read from the memory device at the second supply voltage level in response to decreasing the supply voltage. The supply voltage is increased for the memory device to a third supply voltage level above the second supply voltage level in response to reading the test data. The test data is read from the memory device at the third supply voltage level in response to increasing the supply voltage. The test data written to the memory device at the first supply voltage level is compared to the test data read from the memory device at the third supply voltage level in response to reading the test data from the memory device at the third supply voltage level.
摘要翻译：在第一电源电压电平下为存储器件设置电源电压。响应于设置电源电压，以第一电源电压电平将测试数据写入存储器件。响应于写入测试数据，存储器件的电源电压降低到低于第一电源电压电平的第二电源电压电平。响应于降低电源电压，在第二电源电压电平下从存储器件读取测试数据。响应于读取测试数据，存储器件的电源电压增加到高于第二电源电压电平的第三电源电压电平。响应于增加电源电压，在第三电源电压电平下从存储器件读取测试数据。响应于以第三电源电压从存储器件读取测试数据，将以第一电源电压电平写入存储器件的测试数据与从第三电源电压电平读出的测试数据进行比较。

6. 发明申请

US20090285044A1 TESTING A MEMORY DEVICE HAVING FIELD EFFECT TRANSISTORS SUBJECT TO THRESHOLD VOLTAGE SHIFTS CAUSED BY BIAS TEMPERATURE INSTABILITY 有权
标题翻译：测试具有由偏置温度不稳定性引起的阈值电压变化的场效应晶体管的存储器件
公开(公告)号：US20090285044A1
公开(公告)日：2009-11-19
申请号：US12121560
申请日：2008-05-15
申请人： Nan Chen , Sian-Yee Sean Lee , Seong-Ook Jung , Zhongze Wang
发明人： Nan Chen , Sian-Yee Sean Lee , Seong-Ook Jung , Zhongze Wang
IPC分类号： F21V29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/10 , G11C29/12005
摘要： A supply voltage is set for a memory device at a first supply voltage level. Test data is written to the memory device at the first supply voltage level in response to setting the supply voltage. The supply voltage is decreased for the memory device to a second supply voltage level below the first supply voltage level in response to writing the test data. The test data is read from the memory device at the second supply voltage level in response to decreasing the supply voltage. The supply voltage is increased for the memory device to a third supply voltage level above the second supply voltage level in response to reading the test data. The test data is read from the memory device at the third supply voltage level in response to increasing the supply voltage. The test data written to the memory device at the first supply voltage level is compared to the test data read from the memory device at the third supply voltage level in response to reading the test data from the memory device at the third supply voltage level.
摘要翻译：在第一电源电压电平下为存储器件设置电源电压。响应于设置电源电压，以第一电源电压电平将测试数据写入存储器件。响应于写入测试数据，存储器件的电源电压降低到低于第一电源电压电平的第二电源电压电平。响应于降低电源电压，在第二电源电压电平下从存储器件读取测试数据。响应于读取测试数据，存储器件的电源电压增加到高于第二电源电压电平的第三电源电压电平。响应于增加电源电压，在第三电源电压电平下从存储器件读取测试数据。响应于以第三电源电压从存储器件读取测试数据，将以第一电源电压电平写入存储器件的测试数据与从第三电源电压电平读出的测试数据进行比较。

7. 发明授权

US08558320B2 Systems and methods employing a physically asymmetric semiconductor device having symmetrical electrical behavior 有权
标题翻译：采用具有对称电气行为的物理不对称半导体器件的系统和方法
公开(公告)号：US08558320B2
公开(公告)日：2013-10-15
申请号：US12638557
申请日：2009-12-15
申请人： Haining Yang , Chock H. Gan , Zhongze Wang , Beom-Mo Han
发明人： Haining Yang , Chock H. Gan , Zhongze Wang , Beom-Mo Han
IPC分类号： H01L27/092
CPC分类号： H01L27/0207 , H01L21/823425 , H01L21/823475 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.
摘要翻译：一种集成电路装置，包括彼此平行布置并且在它们之间限定空间的第一细长结构和第二细长结构。集成电路装置还包括分布在第一和第二细长结构之间的空间中的导电结构。导电结构中的至少第一个被放置成比第二细长结构更靠近第一细长结构。导电结构中的至少第二个被放置成比第一细长结构更靠近第二细长结构。

8. 发明申请

US20110140288A1 Systems and Methods Employing a Physically Asymmetric Semiconductor Device Having Symmetrical Electrical Behavior 有权
标题翻译：采用具有对称电气行为的物理不对称半导体器件的系统和方法
公开(公告)号：US20110140288A1
公开(公告)日：2011-06-16
申请号：US12638557
申请日：2009-12-15
申请人： Haining Yang , Chock H. Gan , Zhongze Wang , Beom-Mo Han
发明人： Haining Yang , Chock H. Gan , Zhongze Wang , Beom-Mo Han
IPC分类号： H01L23/50 , H01L21/3205
CPC分类号： H01L27/0207 , H01L21/823425 , H01L21/823475 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.
摘要翻译：一种集成电路装置，包括彼此平行布置并且在它们之间限定空间的第一细长结构和第二细长结构。集成电路装置还包括分布在第一和第二细长结构之间的空间中的导电结构。导电结构中的至少第一个被放置成比第二细长结构更靠近第一细长结构。导电结构中的至少第二个被放置成比第一细长结构更靠近第二细长结构。

9. 发明授权

US09495503B2 Method and apparatus to enable a selective push process during manufacturing to improve performance of a selected circuit of an integrated circuit 有权
标题翻译：在制造期间能够进行选择性推送过程以改善集成电路的选定电路的性能的方法和装置
公开(公告)号：US09495503B2
公开(公告)日：2016-11-15
申请号：US13372160
申请日：2012-02-13
申请人： Jeffrey Herbert Fischer , Manish Garg , Zhongze Wang
发明人： Jeffrey Herbert Fischer , Manish Garg , Zhongze Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.
摘要翻译：提供了用于在设计和制造集成电路期间进行选择性推送处理以改善集成电路的选定电路的性能的方法和装置。一种示例性方法包括识别集成电路布局的关键部分，该集成电路布局定义了具有关键工作频率要求的功能元件，并且在关键部分中设计子电路以使能执行速度推动过程以增加子电路的性能。该方法还可以包括在关键部分和在关键部分之外的集成电路的一部分之间的边界处识别供电节点，时钟供应节点和接口节点中的至少一个。关键部分可以被设计成具有独立于在关键部分之外的集成电路的部分的功率域。

10. 发明授权

US06984570B2 Wafer bonding method of forming silicon-on-insulator comprising integrated circuitry 失效
标题翻译：形成绝缘体上硅的晶片接合方法包括集成电路
公开(公告)号：US06984570B2
公开(公告)日：2006-01-10
申请号：US10735355
申请日：2003-12-12
申请人： Zhongze Wang
发明人： Zhongze Wang
IPC分类号： H01L21/30
CPC分类号： H01L29/66772 , H01L21/76256 , H01L29/78603
摘要： A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing at least a portion of an outer surface of silicon of a device wafer. After the nitridizing, the device wafer is joined with a handle wafer. A method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing an interface of the silicon comprising layer of silicon-on-insulator circuitry with the insulator layer of the silicon-on-insulator circuitry. After the nitridizing, a field effect transistor gate is formed operably proximate the silicon comprising layer. Other methods are disclosed. Integrated circuitry is contemplated regardless of the method of fabrication.
摘要翻译：形成绝缘体上硅包括集成电路的晶片接合方法包括氮化器件晶片的硅的外表面的至少一部分。在氮化之后，器件晶片与处理晶片接合。一种形成绝缘体上硅的方法，包括集成电路包括将包含绝缘体上硅电路的硅层的界面氮化为绝缘体上硅电路的绝缘体层。在氮化之后，场效应晶体管栅极可靠地形成在包含硅的层上。公开了其他方法。无论制造方法如何，都可以考虑集成电路。

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