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1. 发明授权

US09495503B2 Method and apparatus to enable a selective push process during manufacturing to improve performance of a selected circuit of an integrated circuit 有权
标题翻译：在制造期间能够进行选择性推送过程以改善集成电路的选定电路的性能的方法和装置
公开(公告)号：US09495503B2
公开(公告)日：2016-11-15
申请号：US13372160
申请日：2012-02-13
申请人： Jeffrey Herbert Fischer , Manish Garg , Zhongze Wang
发明人： Jeffrey Herbert Fischer , Manish Garg , Zhongze Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.
摘要翻译：提供了用于在设计和制造集成电路期间进行选择性推送处理以改善集成电路的选定电路的性能的方法和装置。一种示例性方法包括识别集成电路布局的关键部分，该集成电路布局定义了具有关键工作频率要求的功能元件，并且在关键部分中设计子电路以使能执行速度推动过程以增加子电路的性能。该方法还可以包括在关键部分和在关键部分之外的集成电路的一部分之间的边界处识别供电节点，时钟供应节点和接口节点中的至少一个。关键部分可以被设计成具有独立于在关键部分之外的集成电路的部分的功率域。

2. 发明申请

US20120256682A1 Method and Apparatus to Enable a Selective Push Process During Manufacturing to Improve Performance of a Selected Circuit of an Integrated Circuit 有权
标题翻译：在制造过程中启用选择性推送过程以改善集成电路的选定电路的性能的方法和装置
公开(公告)号：US20120256682A1
公开(公告)日：2012-10-11
申请号：US13372160
申请日：2012-02-13
申请人： Jeffrey Herbert Fischer , Manish Garg , Zhongze Wang
发明人： Jeffrey Herbert Fischer , Manish Garg , Zhongze Wang
IPC分类号： G06F17/50 , H01L25/00
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.
摘要翻译：提供了用于在设计和制造集成电路期间进行选择性推送处理以改善集成电路的选定电路的性能的方法和装置。一种示例性方法包括识别集成电路布局的关键部分，该集成电路布局定义了具有关键工作频率要求的功能元件，并且在关键部分中设计子电路以使能执行速度推动过程以增加子电路的性能。该方法还可以包括在关键部分和在关键部分之外的集成电路的一部分之间的边界处识别供电节点，时钟供应节点和接口节点中的至少一个。关键部分可以被设计成具有独立于在关键部分之外的集成电路的部分的功率域。

3. 发明授权

US09196330B2 Mimicking multi-voltage domain wordline decoding logic for a memory array 有权
标题翻译：模拟存储器阵列的多电压域字线解码逻辑
公开(公告)号：US09196330B2
公开(公告)日：2015-11-24
申请号：US13424833
申请日：2012-03-20
申请人： Shaoping Ge , Chiaming Chai , Stephen E. Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
发明人： Shaoping Ge , Chiaming Chai , Stephen E. Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
IPC分类号： G11C8/00 , G11C8/08 , G11C7/12 , G11C8/10 , G11C7/22
CPC分类号： G11C8/08 , G11C7/12 , G11C7/22 , G11C7/227 , G11C8/10
摘要： Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.
摘要翻译：公开了用于自适应模拟用于多电压域存储器的字线解码逻辑的系统和方法。在一个实施例中，多电压域存储器包括以高电压域实现的存储器阵列和多电压域控制电路。多电压域控制电路包括产生存储器阵列的字线的多电压域解码逻辑和模拟多电压域解码逻辑以产生伪字线的多电压域模拟逻辑。在一个实施例中，一旦确定了字线，就使用伪字线来触发字线的结束边缘（例如，下降沿）。另外或替代地，伪字线用于产生用于存储器阵列的一个或多个控制信号，例如预充电控制信号和/或读出放大器使能信号。

4. 发明授权

US07761774B2 High speed CAM lookup using stored encoded key 有权
标题翻译：使用存储的编码密钥进行高速CAM查找
公开(公告)号：US07761774B2
公开(公告)日：2010-07-20
申请号：US11262063
申请日：2005-10-28
申请人： Jeffrey Herbert Fischer , Michael ThaiThanh Phan , Chiaming Chai , James Norris Dieffenderfer
发明人： Jeffrey Herbert Fischer , Michael ThaiThanh Phan , Chiaming Chai , James Norris Dieffenderfer
IPC分类号： G11C29/00
CPC分类号： G11C15/00 , G06F12/1027 , G06F2212/652 , G11C15/04
摘要： The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged, the search key is a physical address. The page address portion of the physical address is encoded prior to being stored in a TLB. The page offset bits are encoded in parallel with the TLB access, and concatenated with the encoded TLB entry. If a page address addresses a large memory page size, a plurality of corresponding sub-page addresses may be generated, each addressing a smaller page size. These sub-page addresses may be encoded and stored in a micro TLB. The encoded key and key field are tolerant of single-bit soft errors.
摘要翻译：高速缓存中的CAM的搜索键和关键字段通过至少两个汉明距离进行编码，以通过确保每个不匹配的匹配线由并联的至少两个晶体管放电来增加CAM的速度。在缓存物理标记的地方，搜索关键字是物理地址。物理地址的页地址部分在被存储在TLB中之前被编码。页面偏移位与TLB访问并行编码，并与编码的TLB条目连接。如果页面地址满足大的存储器页面大小，则可以生成多个对应的子页面地址，每个地址寻址较小的页面大小。这些子页地址可以被编码并存储在微型TLB中。编码的密钥和密钥字段容忍单位软错误。

5. 发明授权

US07586772B2 Method and apparatus for aborting content addressable memory search operations 有权
标题翻译：用于中止内容可寻址存储器搜索操作的方法和装置
公开(公告)号：US07586772B2
公开(公告)日：2009-09-08
申请号：US11462457
申请日：2006-08-04
申请人： Chiaming Chai , Jeffrey Herbert Fischer , Michael ThaiThanh Phan
发明人： Chiaming Chai , Jeffrey Herbert Fischer , Michael ThaiThanh Phan
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： Content Addressable Memory (CAM) search operations are aborted in response to a search abort signal, thus preserving previous CAM search results. In one embodiment, a CAM search operation is aborted by activating a local CAM match line in response to a search field provided to a CAM and preventing activation of a global CAM match line associated with the local CAM match line in response to a search abort signal. By preventing activation of global CAM match lines, monotonic storage devices included in a holding register that captures CAM search results are prevented from overwriting previously stored CAM search results.
摘要翻译：响应于搜索中止信号，内容可寻址存储器（CAM）搜索操作被中止，从而保留先前的CAM搜索结果。在一个实施例中，通过响应于提供给CAM的搜索字段来激活本地CAM匹配行来中止CAM搜索操作，并且响应于搜索中止信号阻止与本地CAM匹配行相关联的全局CAM匹配行的激活。通过防止全局CAM匹配线的激活，防止包含在捕获CAM搜索结果的保持寄存器中的单调存储设备覆盖先前存储的CAM搜索结果。

6. 发明授权

US07301384B2 Multimode, uniform-latency clock generation circuit 有权
标题翻译：多模均匀时延产生电路
公开(公告)号：US07301384B2
公开(公告)日：2007-11-27
申请号：US11394557
申请日：2006-03-31
申请人： Fadi Adel Hamdan , Jeffrey Herbert Fischer , William James Goodall, III
发明人： Fadi Adel Hamdan , Jeffrey Herbert Fischer , William James Goodall, III
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A multimode, uniform-latency clock generation circuit (CGC) is described herein. In one example, the multimode, uniform-latency CGC generates a pulse clock signal via a clock generation path responsive to a clock chopping signal being active and generates a phase clock signal via the same clock generation path responsive to the clock chopping signal being inactive. The clock chopping signal is activated responsive to a mode control input signal being in a first state and deactivated responsive to either the mode control input signal being in a second state or a plurality of clock enable signals being inactive. In one or more embodiments, a multimode, uniform-latency CGC is included in a microprocessor for providing pulse clock signals to inter-stage pulsed sequential storage elements when operating in a timing sensitive mode and for providing phase clock signals to the inter-stage pulsed sequential storage elements when operating in a timing insensitive mode.
摘要翻译：本文描述了多模均匀延迟时钟产生电路（CGC）。在一个示例中，多模均衡延迟CGC响应于时钟斩波信号有效而经由时钟产生通路产生脉冲时钟信号，并且响应于时钟斩波信号无效而经由相同的时钟产生通路产生相位时钟信号。响应于处于第一状态的模式控制输入信号来激活时钟斩波信号，并且响应于处于第二状态的模式控制输入信号或多个时钟使能信号无效而停止时钟斩波信号。在一个或多个实施例中，多模均匀延迟CGC被包括在微处理器中，用于当以定时灵敏模式工作时将脉冲时钟信号提供给级间脉冲顺序存储元件，并且用于将相位时钟信号提供给级间脉冲在时序不敏感模式下运行的顺序存储元件。

7. 发明授权

US06556466B2 Method and structure for a CAMRAM cache memory 失效
公开(公告)号：US06556466B2
公开(公告)日：2003-04-29
申请号：US09842953
申请日：2001-04-26
申请人： Chiaming Chai , Jeffrey Herbert Fischer , Michael Thai Thanh Phan
发明人： Chiaming Chai , Jeffrey Herbert Fischer , Michael Thai Thanh Phan
IPC分类号： G11C1500
CPC分类号： G06F12/0893 , G11C15/00
摘要： An improved structure and method of operation are provided wherein a single RAM (random access memory) can be serviced by two CAMs (content addressable memory). This is accomplished by providing first actuating circuitry operably associated with and operatively connecting a first CAM to a selected portion of the RAM and second actuating circuit associated with and operably connecting a second CAM to a second portion of the RAM. The first actuating circuitry includes circuitry to actuate a selected wordline responsive to a CAM search read and RAM search read and circuitry to initiate a CAMRAM index read and index write operably responsive to given control logic. The second circuitry includes circuitry to actuate a selected wordline responsive to a CAM search read and RAM search read responsive to given control logic.

8. 发明授权

US08638153B2 Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width 有权
标题翻译：具有内置电平转换器和可编程上升沿和脉冲宽度的脉冲时钟生成逻辑
公开(公告)号：US08638153B2
公开(公告)日：2014-01-28
申请号：US13433891
申请日：2012-03-29
申请人： Shaoping Ge , Chiaming Chai , Stephen Edward Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
发明人： Shaoping Ge , Chiaming Chai , Stephen Edward Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
IPC分类号： H03K3/00
CPC分类号： G06F1/04 , G11C7/222 , G11C11/417 , G11C11/418 , G11C11/419
摘要： Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.
摘要翻译：用于产生具有可编程边沿和脉冲宽度的脉冲时钟的系统和方法被配置用于不同存储器访问操作的不同需求。脉冲时钟产生电路包括提供脉冲时钟的可编程上升沿延迟的选择性延迟逻辑，提供脉冲时钟可编程脉冲宽度的选择性脉宽扩展逻辑，以及内置电平转换器，脉冲时钟电平。读操作的上升沿延迟被编程为对应于期望的读数组访问延迟，并且用于写操作的脉冲宽度被编程为比读操作的脉冲宽度宽。

9. 发明申请

US20130257498A1 Pulse Clock Generation Logic with Built-in Level Shifter and Programmable Rising Edge and Pulse Width 有权
标题翻译：具有内置电平移位器和可编程上升沿和脉冲宽度的脉冲时钟生成逻辑
公开(公告)号：US20130257498A1
公开(公告)日：2013-10-03
申请号：US13433891
申请日：2012-03-29
申请人： Shaoping Ge , Chiaming Chai , Stephen Edward Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
发明人： Shaoping Ge , Chiaming Chai , Stephen Edward Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
IPC分类号： H03K5/01
CPC分类号： G06F1/04 , G11C7/222 , G11C11/417 , G11C11/418 , G11C11/419
摘要： Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.
摘要翻译：用于产生具有可编程边沿和脉冲宽度的脉冲时钟的系统和方法被配置用于不同存储器访问操作的不同需求。脉冲时钟产生电路包括提供脉冲时钟的可编程上升沿延迟的选择性延迟逻辑，提供脉冲时钟可编程脉冲宽度的选择性脉宽扩展逻辑，以及内置电平转换器，脉冲时钟电平。读操作的上升沿延迟被编程为对应于期望的读数组访问延迟，并且用于写操作的脉冲宽度被编程为比读操作的脉冲宽度宽。

10. 发明申请

US20130182514A1 Mimicking Multi-Voltage Domain Wordline Decoding Logic for a Memory Array 有权
标题翻译：模拟存储器阵列的多电压域字线解码逻辑
公开(公告)号：US20130182514A1
公开(公告)日：2013-07-18
申请号：US13424833
申请日：2012-03-20
申请人： Shaoping Ge , Chiaming Chai , Stephen E. Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
发明人： Shaoping Ge , Chiaming Chai , Stephen E. Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
IPC分类号： G11C7/12 , G11C8/10 , G11C7/00
CPC分类号： G11C8/08 , G11C7/12 , G11C7/22 , G11C7/227 , G11C8/10
摘要： Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.
摘要翻译：公开了用于自适应模拟用于多电压域存储器的字线解码逻辑的系统和方法。在一个实施例中，多电压域存储器包括以高电压域实现的存储器阵列和多电压域控制电路。多电压域控制电路包括生成用于存储器阵列的字线的多电压域解码逻辑和模拟多电压域解码逻辑以产生伪字线的多电压域模拟逻辑。在一个实施例中，一旦确定了字线，就使用伪字线来触发字线的结束边缘（例如，下降沿）。另外或替代地，伪字线用于产生用于存储器阵列的一个或多个控制信号，例如预充电控制信号和/或读出放大器使能信号。

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