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1. 发明授权

US5838895A Fault detection and automatic recovery apparatus or write-read pointers in First-In First-Out 失效
标题翻译：故障检测和自动恢复设备或先进先出的读取指针
公开(公告)号：US5838895A
公开(公告)日：1998-11-17
申请号：US857045
申请日：1997-05-15
申请人： Seong-Do Kim , Hee-Bum Jung , Won-Chul Song
发明人： Seong-Do Kim , Hee-Bum Jung , Won-Chul Song
IPC分类号： G11C29/00 , G06F12/00 , G06F13/00
CPC分类号： G11C29/003
摘要： The present invention relates to a fault detection and automatic recovery apparatus of write-read pointers in FIFO. While storing effective data in a register in writing performance, the apparatus does not unconditionally enable a FULL.sub.-- FLAG signal allotted to the register but confirms the relation of write-read pointers at that time and the EMPTY.sub.-- FLAG signal of a register at which the read pointer is situated and detects the error of FIFO. By selectively enabling the FULL.sub.-- FLAG signal of the register according to the result of detection, it automatically restores the FIFO functions without unnecessary re-initialization or the discontinuation of data transmission attributable thereto.
摘要翻译：本发明涉及FIFO中写入指针的故障检测和自动恢复装置。在写入性能方面将有效数据存储在寄存器中时，该装置不能无条件地使能分配给寄存器的FULL-FLAG信号，而是确认该时刻的读 - 读指针与寄存器的EMPTY-FLAG信号的关系，读指针位于并检测FIFO的错误。通过根据检测结果有选择地启用寄存器的FULL-FLAG信号，它会自动恢复FIFO功能，而无需不必要的重新初始化或中止可归因于其的数据传输。

2. 发明授权

US5886552A Data retiming circuit 失效
标题翻译：数据重新定时电路
公开(公告)号：US5886552A
公开(公告)日：1999-03-23
申请号：US859203
申请日：1997-05-20
申请人： Sang-Hoon Chai , Hee-Bum Jung , Won-Chul Song
发明人： Sang-Hoon Chai , Hee-Bum Jung , Won-Chul Song
IPC分类号： H04L7/033 , H04L7/00
CPC分类号： H04L7/0338
摘要： An improved data retiming circuit which is capable of more effectively retiming an externally inputted data by using a plurality of clocks from a voltage controlled oscillator of a phase-locked loop. The circuit includes a first delay unit for increasing a rising and falling time from an externally inputted data by a predetermined time as much as a clock phase difference, a first data latch unit connected so that the phase from the clock generator can be to correspond with the number of different clocks for latching the data inputted in accordance with the clock, a second delay unit for receiving the data from the first delay unit and for delaying the data so that a clock is selected and coincides with the timing until the output of the clock, a data latch state determination unit for determining the logic signal state of the data latched by the first data latch unit in an analog method, a clock selection unit for logically compares a plurality of clocks inputted and a data state signal outputted from the data latch state determination unit and for selecting a retiming signal, and a second data latch unit for latching the data relayed by the second delay unit in accordance with the retiming clock signal.
摘要翻译：一种改进的数据重定时电路，其能够通过使用来自锁相环的压控振荡器的多个时钟来更有效地重新定时外部输入的数据。该电路包括第一延迟单元，用于将来自外部输入的数据的上升和下降时间增加预定时间多达时钟相位差;第一数据锁存单元，其连接使得来自时钟发生器的相位可以对应于用于锁存根据时钟输入的数据的不同时钟的数量;第二延迟单元，用于从第一延迟单元接收数据，并用于延迟数据，使得选择时钟，并与直到输出的时序一致时钟，数据锁存状态确定单元，用于以模拟方法确定由第一数据锁存单元锁存的数据的逻辑信号状态;时钟选择单元，用于逻辑地比较输入的多个时钟和从数据输出的数据状态信号锁存状态确定单元并用于选择重新定时信号;以及第二数据锁存单元，用于锁存由第二延迟单元中继的数据，重新定时时钟信号。

3. 发明授权

US5600186A Capacitor voltage divider circuit 失效
标题翻译：电容分压电路
公开(公告)号：US5600186A
公开(公告)日：1997-02-04
申请号：US350020
申请日：1994-11-29
申请人： Won-Chul Song , Chang-Jun Oh , Jong-Ryul Lee , Hae-Wook Choi , Bang-Sup Song
发明人： Won-Chul Song , Chang-Jun Oh , Jong-Ryul Lee , Hae-Wook Choi , Bang-Sup Song
IPC分类号： G05F1/10 , H03M1/36 , H03M1/74 , H01H47/00
CPC分类号： H03M1/361 , Y10T307/826
摘要： A capacitor type voltage divider circuit is disclosed. The divider has a plurality of reference voltage signals applied from an external source. A plurality of switching sections are provided for switching the reference voltage signals from the source in response to first and second clock signals. A plurality of dividing sections are provided which are each comprised of two capacitors for dividing the voltage signals from the switching section into a predetermined value. With the dividing circuit, precise levels of reference voltage signals are obtained and power consumption is low without an increase in size or lowering of operational speed.
摘要翻译：公开了一种电容式分压电路。分压器具有从外部源施加的多个参考电压信号。多个开关部分被提供用于响应于第一和第二时钟信号从源极切换参考电压信号。提供多个分割部分，每个分割部分包括用于将来自切换部分的电压信号分成预定值的两个电容器。通过分频电路，可以获得精确的参考电压信号，并且功耗低，而不会增加尺寸或降低运行速度。

4. 发明授权

US5600269A Low power consumption comparator circuit 失效
标题翻译：低功耗比较电路
公开(公告)号：US5600269A
公开(公告)日：1997-02-04
申请号：US352830
申请日：1994-12-02
申请人： Won-Chul Song , Chang-Jun Oh , Jong-Ryul Lee , Hae-Wook Choi , Bang-Sup Song
发明人： Won-Chul Song , Chang-Jun Oh , Jong-Ryul Lee , Hae-Wook Choi , Bang-Sup Song
IPC分类号： G11C11/409 , G11C7/06 , H03F3/45 , H03K3/356 , H03K5/08 , H03K5/24 , H03M1/34 , G11C7/00
CPC分类号： H03K3/356156 , G11C7/062 , H03F3/45076 , H03K3/356139 , H03K3/356191 , H03K5/2481 , H03K5/249
摘要： Disclosed is a low power-consumption type comparator circuit having two input terminals for receiving two input signals, one of which is an input reference signal and the other of which is an input comparison signal, and two output terminals, the circuit comprising signal converting portion for converting the input signals into current signals, respectively; switching portion for controlling transmission of the current signals to output terminals of the circuit in response to a latch signal indicating a latch operation or a normal operation of the circuit; high level holding portion for maintaining each voltage level of the output terminals to a logical high-state only when the latch operation of the circuit is not performed; amplifying/determining portion for amplifying the current signals and determining logical level of the input comparison signal; and output feedback portion for receiving output signals of the output terminals and enabling to make a current flowing in the circuit to a zero-state, only while the circuit is at the latch operation. Since a current-consumption is at a zero-state during the normal operation of the comparator circuit, the comparator circuit has a low power-consumption characteristic.
摘要翻译：公开了一种低功耗型比较器电路，具有用于接收两个输入信号的两个输入端，其中一个输入信号是输入参考信号，另一个是输入比较信号，两个输出端包括信号转换部分用于将输入信号分别转换为电流信号; 切换部分，用于响应于指示电路的锁存操作或正常操作的锁存信号，控制电流信号传输到电路的输出端; 高电平保持部分，用于仅当不执行电路的锁存操作时，将输出端子的每个电压电平维持为逻辑高电平状态; 放大/确定部分，用于放大当前信号并确定输入比较信号的逻辑电平; 以及输出反馈部分，用于接收输出端子的输出信号，并且仅在电路处于锁存操作时才能使电流在电路中流动到零状态。由于在比较器电路的正常工作期间电流消耗处于零状态，因此比较器电路具有低功耗特性。

5. 发明授权

US6011425A CMOS offset trimming circuit and offset generation circuit 失效
标题翻译： CMOS偏移调整电路和偏移生成电路
公开(公告)号：US6011425A
公开(公告)日：2000-01-04
申请号：US893459
申请日：1997-07-11
申请人： Chang-Jun Oh , Ook Kim , Jong-Kee Kwon , Jong-Ryul Lee , Won-Chul Song , Kyung-Soo Kim
发明人： Chang-Jun Oh , Ook Kim , Jong-Kee Kwon , Jong-Ryul Lee , Won-Chul Song , Kyung-Soo Kim
IPC分类号： H03K19/00 , G11C17/18 , H01H37/76
CPC分类号： G11C17/18
摘要： A CMOS offset trimming circuit and offset generation circuit for obtaining the corrected optimum offset value for correcting the offset generated in the CMOS analog circuit. An offset trimming circuit comprises a flip-flop for loading a data to be used for obtaining an optimum offset value or a data to be trimmed according to an input clock, a fuse circuit for setting the circuit with a corrected optimum offset value obtained in a corresponding mode by receiving the data loaded on the flip-flop and the mode selection signal as an input signal, and a selection logic circuit for outputting a selected signal as a trimming output signal by selecting one from the group consisting of the data loaded on the flip-flop and the data output from the fuse circuit according to the operation mode.
摘要翻译： CMOS偏移调整电路和偏移生成电路，用于获得用于校正在CMOS模拟电路中产生的偏移的校正的最佳偏移值。偏移修整电路包括用于根据输入时钟加载要用于获得最佳偏移值的数据或要修整的数据的触发器，用于设置具有校正的最佳偏移值的电路的熔丝电路，通过接收加载在触发器上的数据和模式选择信号作为输入信号的相应模式，以及选择逻辑电路，用于通过从由加载在所述触发器上的数据组合的组中选择一个来选择所选择的信号作为微调输出信号触发器和根据操作模式从熔丝电路输出的数据。

6. 发明授权

US5886550A Integrated circuit built-in type supply power delay circuit 失效
标题翻译：集成电路内置式电源延时电路
公开(公告)号：US5886550A
公开(公告)日：1999-03-23
申请号：US877408
申请日：1997-06-16
申请人： Jong-Kee Kwon , Gyu-Dong Kim , Ook Kim , Chang-Jun Oh , Jong-Ryul Lee , Won-Chul Song , Kyung-Soo Kim
发明人： Jong-Kee Kwon , Gyu-Dong Kim , Ook Kim , Chang-Jun Oh , Jong-Ryul Lee , Won-Chul Song , Kyung-Soo Kim
IPC分类号： G11C5/14 , H03K17/22
CPC分类号： H03K17/223
摘要： An integrated circuit built-in type power delay circuit which is capable of supplying a stable supply power to each circuit of the integrated circuit by generating a supply power control signal voltage after a predetermined time. The circuit includes a receiving unit for receiving a supply voltage VDD and charging the same, a supplying unit for supplying a current, an inverting unit for inverting an output value from the charging unit, a switching unit controlled in accordance with an output value from the inverting unit for switching an output from the current supply unit, a current regenerating unit for receiving a control of the switching unit and discharging an output value from the charging unit, an electric potential value conversion unit controlled by an output value from the inverting unit for converting an output value from the charging unit into a low level, and a buffering unit for receiving an output value from the inverting unit for buffering the output value and outputting a non-inverted signal.
摘要翻译：一种集成电路内置型功率延迟电路，其能够通过在预定时间之后产生电源功率控制信号电压来向集成电路的每个电路提供稳定的供电。该电路包括：接收单元，用于接收电源电压VDD并对其进行充电;提供单元，用于提供电流;反相单元，用于反转来自充电单元的输出值;开关单元，根据来自用于切换来自电流供应单元的输出的反相单元，用于接收开关单元的控制并从充电单元放电输出值的电流再生单元，由来自反相单元的输出值控制的电位值转换单元，将来自充电单元的输出值转换为低电平;以及缓冲单元，用于从反相单元接收输出值，用于缓冲输出值并输出非反相信号。

7. 发明授权

US5818306A Voltage control oscillation circuit using CMOS 失效
标题翻译：使用CMOS的电压控制振荡电路
公开(公告)号：US5818306A
公开(公告)日：1998-10-06
申请号：US892938
申请日：1997-07-15
申请人： Jong-Ryul Lee , Ook Kim , Jong-Kee Kwon , Chang-Jun Oh , Won-Chul Song , Kyung-Soo Kim
发明人： Jong-Ryul Lee , Ook Kim , Jong-Kee Kwon , Chang-Jun Oh , Won-Chul Song , Kyung-Soo Kim
IPC分类号： H03B5/00 , H03B1/00 , H03B1/04 , H03B5/12 , H03L5/00
CPC分类号： H03L5/00 , H03B5/1209 , H03B5/1215 , H03B5/1221 , H03B5/1228 , H03B5/1243 , H03B2200/0066 , H03B2200/0082 , H03B2200/0086 , H03B2200/0088 , H03B2200/0098 , H03B2201/0208 , H03B2202/012 , H03B2202/06
摘要： A voltage control oscillation circuit for a CMOS which is capable of reducing phase noise and power consumption by adapting a voltage amplitude control loop and a common mode feedback circuit to a conventional LC-tank circuit. The circuit includes an LC-tank oscillation unit for outputting an oscillation voltage, an output common mode feedback unit for receiving an output from the LC-tank oscillation unit and eliminating a common mode noise of the output, and a voltage amplitude control unit for controlling a bias current of the LC-tank oscillation unit in accordance with a voltage difference at both ends of an LC-tank oscillation terminal which voltage is applied thereto through the output common mode feedback unit, for thus controlling the amount of an oscillation voltage.
摘要翻译：一种用于CMOS的电压控制振荡电路，其能够通过使电压幅度控制回路和共模反馈电路适应于传统的LC槽电路来降低相位噪声和功耗。电路包括用于输出振荡电压的LC槽振荡单元，用于接收来自LC槽振荡单元的输出并消除输出的共模噪声的输出共模反馈单元和用于控制的电压幅度控制单元根据通过输出共模反馈单元向其施加电压的LC槽振荡端子的两端的电压差，LC槽振荡单元的偏置电流，从而控制振荡电压的量。

8. 发明授权

US6121818A Mixer using replica voltage-current converter 失效
标题翻译：混频器使用复制电压电流转换器
公开(公告)号：US6121818A
公开(公告)日：2000-09-19
申请号：US970350
申请日：1997-11-14
申请人： Ook Kim , Jong-Kee Kwon , Jong-Ryul Lee , Chang-Jun Oh , Won-Chul Song
发明人： Ook Kim , Jong-Kee Kwon , Jong-Ryul Lee , Chang-Jun Oh , Won-Chul Song
IPC分类号： H03D7/00 , H03D7/14 , G06F7/44
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D2200/0088
摘要： The present invention discloses a mixer using a replica voltage-current converter, and more particularly a mixer using the replica voltage-current (V-I) converter of the present invention, which feedbacks the output current of the replica voltage-current converter using an additional amplifier so as to improve the linearity thereof by the gain of the amplifier because the conventional mixer operating at a high speed dissipates a lot of electrical power to have low output impedance.
摘要翻译：本发明公开了一种使用复制电压 - 电流转换器的混频器，特别是使用本发明的复制电压 - 电流（VI）转换器的混频器，其使用附加放大器来反馈复制电压 - 电流转换器的输出电流以便通过放大器的增益来提高其线性度，因为常规的混频器以高速度运行，将大量的电能消耗到具有低的输出阻抗。

9. 发明授权

US5656955A Low power output buffer circuit 失效
标题翻译：低功率输出缓冲电路
公开(公告)号：US5656955A
公开(公告)日：1997-08-12
申请号：US555854
申请日：1995-11-13
申请人： Sang-Hoon Chai , Won-Chul Song , Hoon-Bock Lee , Chang-Sik Yu , Won-Chan Kim
发明人： Sang-Hoon Chai , Won-Chul Song , Hoon-Bock Lee , Chang-Sik Yu , Won-Chan Kim
IPC分类号： H03K19/00 , H03K19/0185 , H03K19/0944
CPC分类号： H03K19/018528
摘要： A low power output buffer circuit for outputting an Emitter Coupled Logic(ECL) signal or Pseudo ECL(PECL) signal using a CMOS device is disclosed. The prior art differential output buffer circuit is comprised of two independent output buffer circuits and each output buffer circuit utilizes 50 ohms of the load resistors, having 20 mW of current to be applied to the circuit, which requires 100 mW of total consumptive power to operate the entire circuit. According to the present invention, a simplified output buffer circuit can be constructed by connecting 100 ohms of load resistors having a center tap to ground to two pads, which reduces half of the consumptive power as compared to that in the prior art circuit.
摘要翻译：公开了一种用于使用CMOS器件输出发射极耦合逻辑（ECL）信号或伪ECL（PECL）信号的低功率输出缓冲电路。现有技术的差分输出缓冲电路由两个独立的输出缓冲电路组成，每个输出缓冲电路利用50欧姆的负载电阻，其中20mW的电流被施加到电路上，这需要100mW的总消耗功率来操作整个电路。根据本发明，通过将具有中心抽头的100欧姆的负载电阻器连接到两个焊盘，可以构造简化的输出缓冲电路，与现有技术的电路相比，其减少了一半的消耗功率。

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