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1. 发明授权

US06584212B1 Apparatus for motion estimation with control part implemented by state transition diagram 有权
标题翻译：用于通过状态转换图实现的控制部分的运动估计装置
公开(公告)号：US06584212B1
公开(公告)日：2003-06-24
申请号：US09475224
申请日：1999-12-30
申请人： Seong Mo Park , Jin Jong Cha , Han Jin Cho
发明人： Seong Mo Park , Jin Jong Cha , Han Jin Cho
IPC分类号： G06K900
CPC分类号： H04N19/533 , G06T7/238 , G06T2200/28 , H04N19/43
摘要： An apparatus for motion estimation with control part implemented by state transition diagram without adding delay circuits to processing elements, and capable of maintaining a regular data flow and easily implementing hardware to improve a power consume and speed is disclosed. The apparatus comprises a first and second storage parts for storing data; a measurement part for finding an absolute difference between the data; a step decision part for determining a minimum value; and a control part implemented by state transition diagram.
摘要翻译：公开了一种用于通过状态转移图实现的具有控制部分的运动估计的装置，而不向处理元件添加延迟电路，并且能够保持规则的数据流并且容易地实现硬件以提高功耗和速度。该装置包括用于存储数据的第一和第二存储部件; 用于求出数据之间的绝对差的测量部分; 用于确定最小值的步骤确定部分; 以及通过状态转换图实现的控制部分。

2. 发明授权

US06201487B1 Error detecting circuit in a line length decoding system 有权
标题翻译：线路长度解码系统中的错误检测电路
公开(公告)号：US06201487B1
公开(公告)日：2001-03-13
申请号：US09368347
申请日：1999-08-05
申请人： Seong Mo Park , Jin Jong Cha , Han Jin Cho
发明人： Seong Mo Park , Jin Jong Cha , Han Jin Cho
IPC分类号： H03M740
CPC分类号： H03M7/46
摘要： An error detection circuit for detecting errors occurring in a data obtained by decoding a compressed image data block by block in a line length decoding system, includes a first storage device for temporarily storing the run representing the number of zeros (‘0’s) in the compressed image data and an EOB signal externally inputted, a selection signal generator for generating a first and a second selection signal in response to the EOB signal supplied from the first storage device, a first selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the first selection signal, a second selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the second selection signal, a reference value generator for generating a reference value based on the output signal of the first selection circuit according to an operation control signal externally inputted, accumulator for accumulating the output of the second selection circuit based on the feedback signal from a second storage device, the second storage device temporarily storing the output of the accumulator, and an error detector for detecting the errors based on the reference value and the output of the second storage device.
摘要翻译：一种误差检测电路，用于检测通过在行长解码系统中逐块解码压缩图像数据而获得的数据中发生的错误，包括：第一存储装置，用于临时存储表示压缩的零数量（“0”）的运行图像数据和外部输入的EOB信号，响应于从第一存储装置提供的EOB信号产生第一和第二选择信号的选择信号发生器，用于选择性地传送由第一存储装置提供的运行的第一选择电路或接地信号，第二选择电路，用于根据第二选择信号选择性地传送由第一存储装置提供的运行或接地信号;参考值发生器，用于基于第一选择信号的输出信号产生参考值; 第一选择电路根据外部输入的操作控制信号，蓄电池基于来自第二存储装置的反馈信号累积第二选择电路的输出，第二存储装置临时存储累加器的输出，以及错误检测器，用于基于参考值和第二选择电路的输出检测错误储存设备。

3. 发明授权

US07830959B2 Apparatus and method for performing intra prediction for image decoder 有权
标题翻译：用于对图像解码器进行帧内预测的装置和方法
公开(公告)号：US07830959B2
公开(公告)日：2010-11-09
申请号：US10876739
申请日：2004-06-28
申请人： Seong Mo Park , Seung Chul Kim , Mi Young Lee , Han Jin Cho , Jong Dae Kim
发明人： Seong Mo Park , Seung Chul Kim , Mi Young Lee , Han Jin Cho , Jong Dae Kim
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04
CPC分类号： H04N19/436 , H04N19/105 , H04N19/186 , H04N19/423 , H04N19/44 , H04N19/593
摘要： Provided is an apparatus and method for performing intra prediction for an image decoder, in which by use of horizontal/vertical blocks adjacent to image data input from an external device, the intra prediction is performed in parallel with respect to 16×16 luminance component and 4×4 luminance component of the image data and then with respect to chrominance component, thereby maximizing efficiency of system to not only reduce execution time and hardware cost but also increase processing speed.
摘要翻译：提供了一种用于对图像解码器进行帧内预测的装置和方法，其中通过使用与从外部设备输入的图像数据相邻的水平/垂直块，相对于16×16亮度分量并行执行帧内预测，图像数据的4×4亮度分量，然后相对于色度分量，从而最大化系统的效率，不仅减少了执行时间和硬件成本，而且提高了处理速度。

4. 发明授权

US08188801B2 Delay circuit for low power ring oscillator 失效
标题翻译：低功耗环形振荡器的延迟电路
公开(公告)号：US08188801B2
公开(公告)日：2012-05-29
申请号：US12878476
申请日：2010-09-09
申请人： Myeung Su Kim , Han Jin Cho , Joon Hyung Lim , Kyung Hee Hong , Yong Il Kwon
发明人： Myeung Su Kim , Han Jin Cho , Joon Hyung Lim , Kyung Hee Hong , Yong Il Kwon
IPC分类号： H03K3/03
CPC分类号： H03K3/0322 , H03K3/012
摘要： Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1−; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2−; a differential output terminal that outputs differential output signals Vout+ and Vout− generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.
摘要翻译：这里公开了一种用于低功率环形振荡器的延迟电路。延迟电路包括：一对N型晶体管，其接收第一差分输入信号Vin1 +和Vin1-; 一对P型晶体管，接收第二差分输入信号Vin2 +和Vin2-; 差分输出端子，其输出从所述一对N型晶体管和所述一对P型晶体管产生的差分输出信号Vout +和Vout-; N型检测器，其向所述一对N型晶体管提供体电压; 以及向该P型晶体管对提供体电压的P型检测器。

5. 发明申请

US20100150041A1 WIRELESS COMMUNICATION APPARATUS HAVING SELF SENSING FUNCTION 有权
标题翻译：具有自我感应功能的无线通信设备
公开(公告)号：US20100150041A1
公开(公告)日：2010-06-17
申请号：US12430313
申请日：2009-04-27
申请人： Joon Hyung LIM , Tah Joon Park , Han Jin Cho , Myeung Su Kim , Sang Hoon Hwang , Kyung Hee Hong , Yong Il Kwon
发明人： Joon Hyung LIM , Tah Joon Park , Han Jin Cho , Myeung Su Kim , Sang Hoon Hwang , Kyung Hee Hong , Yong Il Kwon
IPC分类号： G08C17/00
CPC分类号： H04Q9/02 , H04Q2209/43 , H04Q2209/883
摘要： Disclosed is a wireless communication apparatus having a self sensing function, which can detect an object by use of a wake-up function without employing a separate sensor. The wireless communication apparatus includes a communication unit wirelessly communicating with a server forming a wireless network, and a wake-up unit waking up the communication unit under the control of the server when the communication unit is in sleep mode, and sensing the presence of an object within a preset communication range according to a reflection signal, which is a signal reflected by the object after being transmitted from the communication unit.
摘要翻译：公开了一种具有自感功能的无线通信装置，其可以通过使用唤醒功能而不使用单独的传感器来检测对象。该无线通信装置包括与形成无线网络的服务器无线通信的通信单元，以及当通信单元处于睡眠模式时，在服务器的控制下唤醒通信单元的唤醒单元，并且感测到根据反射信号在预设通信范围内对象，该反射信号是从通信单元发送之后由对象反射的信号。

6. 发明授权

US07554355B2 Crossbar switch architecture for multi-processor SoC platform 有权
标题翻译：交叉开关架构为多处理器SoC平台
公开(公告)号：US07554355B2
公开(公告)日：2009-06-30
申请号：US11607515
申请日：2006-12-01
申请人： June Young Chang , Han Jin Cho
发明人： June Young Chang , Han Jin Cho
IPC分类号： H04L12/50 , H03K17/00
CPC分类号： H04L49/101 , H04L49/15 , H04L49/45
摘要： Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.
摘要翻译：提供了一种适用于多处理器片上系统（SoC）平台的交叉开关架构，其包括能够进行高速数据传输的多个主机和从机，从而允许其中的主机或从机的数量容易增加并具有简单的控制结构。交叉开关架构包括以行和列组成的矩阵形式连接的2x1多路复用器。 2×1复用器各自具有一个输入线，与同一行前列的多路复用器的输出线连接，另一条输入线与包括相应多路复用器的列的输入/输出线连接，另一条输入线与每行最后一列的多路复用器与该行的输入/输出线连接。

7. 发明授权

US08630217B2 Wireless communications terminal having RF direct wakeup function and wakeup method thereof 有权
标题翻译：具有RF直接唤醒功能的无线通信终端及其唤醒方法
公开(公告)号：US08630217B2
公开(公告)日：2014-01-14
申请号：US13342676
申请日：2012-01-03
申请人： Han Jin Cho , Jae Hyung Lee , Myeung Su Kim , Joon Hyung Lim , Tah Joon Park
发明人： Han Jin Cho , Jae Hyung Lee , Myeung Su Kim , Joon Hyung Lim , Tah Joon Park
IPC分类号： H04W52/02
CPC分类号： H04W52/0235 , Y02D70/166
摘要： A wireless communications terminal includes: an RF wake-up detection unit detecting a first RF signal including an RF ID for waking up; and a wireless communications unit waking up when the RF ID included in the first RF signal detected by the RF wake-up detection unit matches a pre-set reference ID in a sleep mode.
摘要翻译：无线通信终端包括：RF唤醒检测单元，检测包括用于唤醒的RF ID的第一RF信号; 以及当由所述RF唤醒检测单元检测到的所述第一RF信号中包含的RF ID与睡眠模式中的预设参考ID匹配时，所述无线通信单元被唤醒。

8. 发明申请

US20090147841A1 DISTRIBUTED VIDEO CODING APPARATUS AND METHOD CAPABLE OF CONTROLLING ENCODING RATE 失效
标题翻译：分布式视频编码设备和能够控制编码速率的方法
公开(公告)号：US20090147841A1
公开(公告)日：2009-06-11
申请号：US12142708
申请日：2008-06-19
申请人： June Young CHANG , Han Jin Cho , Guee Sang Lee , Young Hwan Bae , In San Jeon , Won Jong Kim , Mi Young Lee , Ju Yeob Kim
发明人： June Young CHANG , Han Jin Cho , Guee Sang Lee , Young Hwan Bae , In San Jeon , Won Jong Kim , Mi Young Lee , Ju Yeob Kim
IPC分类号： H04B1/66
CPC分类号： H04N19/137 , H04N19/115 , H04N19/61
摘要： There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.
摘要翻译：提供了一种能够控制编码率的分布式视频编码装置和方法，该装置包括：编码关键帧并输出编码关键帧的比特流的帧内编码器; 编码器速率控制（ERC）模块，通过使用运动复杂度和比特率之间的相关性，根据当前Wyner-Ziv（WZ）帧的运动复杂度来计算比特率; 以及通过在ERC模块处计算出的比特率编码当前WZ帧并输出编码的WZ比特流的turbo编码器。

9. 发明申请

US20070126474A1 Crossbar switch architecture for multi-processor SoC platform 有权
标题翻译：交叉开关架构为多处理器SoC平台
公开(公告)号：US20070126474A1
公开(公告)日：2007-06-07
申请号：US11607515
申请日：2006-12-01
申请人： June Young Chang , Han Jin Cho
发明人： June Young Chang , Han Jin Cho
IPC分类号： H03K19/173
CPC分类号： H04L49/101 , H04L49/15 , H04L49/45
摘要： Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.
摘要翻译：提供了一种适用于多处理器片上系统（SoC）平台的交叉开关架构，其包括能够进行高速数据传输的多个主机和从机，从而允许其中的主机或从机的数量容易增加并具有简单的控制结构。交叉开关架构包括以行和列组成的矩阵形式连接的2x1多路复用器。 2×1复用器各自具有一个输入线，与同一行前列的多路复用器的输出线连接，另一条输入线与包括相应多路复用器的列的输入/输出线连接，另一条输入线与每行最后一列的多路复用器与该行的输入/输出线连接。

10. 发明授权

US07020832B2 Turbo decoder and its calculation methods having a state metric 失效
公开(公告)号：US07020832B2
公开(公告)日：2006-03-28
申请号：US10039005
申请日：2001-12-31
申请人： In San Jeon , Hyuk Kim , Woo Seok Yang , Kyung Soo Kim , Whan Woo Kim , Han Jin Cho
发明人： In San Jeon , Hyuk Kim , Woo Seok Yang , Kyung Soo Kim , Whan Woo Kim , Han Jin Cho
IPC分类号： H03M13/03
CPC分类号： H03M13/3922 , H03M13/2957 , H03M13/6502 , H03M13/6505
摘要： The present invention relates to a turbo decoder having a state metric, a calculating method using the turbo decoder and a computer-readable recoding medium for executing a calculation method implemented to the turbo decoder. The turbo decoder includes branch metric calculation unit, state metric calculation unit and log likelihood ratio calculation unit. The present invention may reduce calculation steps by simplifying a conventional turbo decode algorithm, reducing a size of a hardware, which the turbo decoder can be implemented in as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The present invention can be implemented in an error correction in wireless communication system and satellite communication system.

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