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1. 发明授权

US07785951B2 Methods of forming integrated circuit devices having tensile and compressive stress layers therein and devices formed thereby 有权
标题翻译：形成其中具有拉伸和压应力层的集成电路器件的方法以及由此形成的器件
公开(公告)号：US07785951B2
公开(公告)日：2010-08-31
申请号：US11831223
申请日：2007-07-31
申请人： Seo-woo Nam , Il-young Yoon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
发明人： Seo-woo Nam , Il-young Yoon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/31053 , H01L21/3185 , H01L21/823807
摘要： Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.
摘要翻译：形成集成电路器件的方法包括在半导体衬底上形成第一，第二和第三栅电极。提供了覆盖第一栅电极和第三栅电极的至少第一部分的第一应力膜。第一应力膜具有足够高的内部应力特性，以在与第一栅电极相对延伸的半导体衬底的第一部分中赋予净压应力。还提供了第二应力膜。第二应力膜覆盖第二栅电极和第三栅电极的至少第二部分。第二应力膜具有足够高的内部应力特性，以在与第二栅电极相对延伸的半导体衬底的第二部分中施加净拉伸应力。第二应力膜具有在与第三栅电极相邻的位置处与第一应力膜的上表面共面的上表面。

2. 发明申请

US20080081476A1 Methods of Forming Integrated Circuit Devices Having Tensile and Compressive Stress Layers Therein and Devices Formed Thereby 有权
标题翻译：形成具有拉伸和压缩应力层的集成电路器件的方法和由此形成的器件
公开(公告)号：US20080081476A1
公开(公告)日：2008-04-03
申请号：US11831223
申请日：2007-07-31
申请人： Seo-woo Nam , Il-young Yoon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
发明人： Seo-woo Nam , Il-young Yoon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
IPC分类号： H01L21/302 , H01L21/31
CPC分类号： H01L29/7843 , H01L21/31053 , H01L21/3185 , H01L21/823807
摘要： Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.
摘要翻译：形成集成电路器件的方法包括在半导体衬底上形成第一，第二和第三栅电极。提供了覆盖第一栅电极和第三栅电极的至少第一部分的第一应力膜。第一应力膜具有足够高的内部应力特性，以在与第一栅电极相对延伸的半导体衬底的第一部分中赋予净压应力。还提供了第二应力膜。第二应力膜覆盖第二栅电极和第三栅电极的至少第二部分。第二应力膜具有足够高的内部应力特性，以在与第二栅电极相对延伸的半导体衬底的第二部分中施加净拉伸应力。第二应力膜具有在与第三栅电极相邻的位置处与第一应力膜的上表面共面的上表面。

3. 发明授权

US07902609B2 Semiconductor devices including multiple stress films in interface area 失效
标题翻译：半导体器件包括界面区域中的多个应力膜
公开(公告)号：US07902609B2
公开(公告)日：2011-03-08
申请号：US12621079
申请日：2009-11-18
申请人： Seo-woo Nam , Ki-chul Kim , Young-joon Moon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
发明人： Seo-woo Nam , Ki-chul Kim , Young-joon Moon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
IPC分类号： H01L23/62
CPC分类号： H01L21/823412 , H01L21/823807 , H01L27/088 , H01L27/092 , H01L29/665 , H01L29/6659 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.
摘要翻译：半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和第二晶体管区域并具有第三栅电极。第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。还描述了相关方法。

4. 发明授权

US07642148B2 Methods of producing semiconductor devices including multiple stress films in interface area 失效
标题翻译：在界面区域生产包括多个应力膜的半导体器件的方法
公开(公告)号：US07642148B2
公开(公告)日：2010-01-05
申请号：US11851500
申请日：2007-09-07
申请人： Seo-woo Nam , Ki-chul Kim , Young-joon Moon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
发明人： Seo-woo Nam , Ki-chul Kim , Young-joon Moon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823412 , H01L21/823807 , H01L27/088 , H01L27/092 , H01L29/665 , H01L29/6659 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.
摘要翻译：半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和第二晶体管区域并具有第三栅电极。第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。还描述了相关方法。

5. 发明申请

US20100065919A1 Semiconductor Devices Including Multiple Stress Films in Interface Area 失效
标题翻译：在接口区域包括多个应力薄膜的半导体器件
公开(公告)号：US20100065919A1
公开(公告)日：2010-03-18
申请号：US12621079
申请日：2009-11-18
申请人： Seo-woo Nam , Ki-chul Kim , Young-joon Moon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
发明人： Seo-woo Nam , Ki-chul Kim , Young-joon Moon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
IPC分类号： H01L27/092
CPC分类号： H01L21/823412 , H01L21/823807 , H01L27/088 , H01L27/092 , H01L29/665 , H01L29/6659 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.
摘要翻译：半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和第二晶体管区域并具有第三栅电极。第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。还描述了相关方法。

6. 发明申请

US20080079087A1 SEMICONDUCTOR DEVICES INCLUDING MULTIPLE STRESS FILMS IN INTERFACE AREA AND METHODS OF PRODUCING THE SAME 失效
标题翻译：在界面中包括多个应力膜的半导体器件及其生产方法
公开(公告)号：US20080079087A1
公开(公告)日：2008-04-03
申请号：US11851500
申请日：2007-09-07
申请人： Seo-woo Nam , Ki-chul Kim , Young-joon Moon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
发明人： Seo-woo Nam , Ki-chul Kim , Young-joon Moon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823412 , H01L21/823807 , H01L27/088 , H01L27/092 , H01L29/665 , H01L29/6659 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.
摘要翻译：半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和第二晶体管区域并具有第三栅电极。第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。还描述了相关方法。

7. 发明申请

US20080272436A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080272436A1
公开(公告)日：2008-11-06
申请号：US11853187
申请日：2007-09-11
申请人： Seo-woo Nam , Young-joon Moon , Hong-jae Shin , Nae-in Lee
发明人： Seo-woo Nam , Young-joon Moon , Hong-jae Shin , Nae-in Lee
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/283
CPC分类号： H01L21/823807 , H01L21/76802 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/823871 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film. The semiconductor device further includes a plurality of first contact holes formed through the interlayer insulating film and the first stress film in the first transistor area to expose the first gate electrode and the first source/drain areas, a plurality of second contact holes formed through the interlayer insulating film and the second stress film in the second transistor area to expose the second gate electrode and the second source/drain areas, and a third contact hole formed through the interlayer insulating film, the second stress film, and the first stress film in the interface area to expose the third gate electrode. A depth of a recessed portion of an upper side of the third gate electrode in which the third contact hole is formed is equal to or larger than a depth of a recessed portion of an upper side of the first gate electrode in which the first contact hole is formed.
摘要翻译：半导体器件包括覆盖第一栅电极的第一应力膜和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅电极的至少一部分，覆盖第二栅电极的第二应力膜和第二应力膜第二晶体管区域的源极/漏极区域，并且与界面区域的第三栅电极上的第一应力膜的至少一部分重叠，以及形成在第一和第二应力膜上的层间绝缘膜。半导体器件还包括多个通过层间绝缘膜形成的第一接触孔和第一晶体管区域中的第一应力膜，以暴露第一栅极电极和第一源极/漏极区域，形成多个第二接触孔层间绝缘膜和第二晶体管区域中的第二应力膜，以暴露第二栅电极和第二源极/漏极区，以及通过层间绝缘膜，第二应力膜和第一应力膜形成的第三接触孔暴露第三栅电极的界面区域。形成第三接触孔的第三栅电极的上侧的凹部的深度等于或大于第一栅电极的上侧的凹部的深度，其中第一接触孔形成了。

8. 发明授权

US07759185B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07759185B2
公开(公告)日：2010-07-20
申请号：US11853187
申请日：2007-09-11
申请人： Seo-woo Nam , Young-joon Moon , Hong-jae Shin , Nae-in Lee
发明人： Seo-woo Nam , Young-joon Moon , Hong-jae Shin , Nae-in Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76802 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/823871 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film. The semiconductor device further includes a plurality of first contact holes formed through the interlayer insulating film and the first stress film in the first transistor area to expose the first gate electrode and the first source/drain areas, a plurality of second contact holes formed through the interlayer insulating film and the second stress film in the second transistor area to expose the second gate electrode and the second source/drain areas, and a third contact hole formed through the interlayer insulating film, the second stress film, and the first stress film in the interface area to expose the third gate electrode. A depth of a recessed portion of an upper side of the third gate electrode in which the third contact hole is formed is equal to or larger than a depth of a recessed portion of an upper side of the first gate electrode in which the first contact hole is formed.
摘要翻译：半导体器件包括覆盖第一栅电极的第一应力膜和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅电极的至少一部分，覆盖第二栅电极的第二应力膜和第二应力膜第二晶体管区域的源极/漏极区域，并且与界面区域的第三栅电极上的第一应力膜的至少一部分重叠，以及形成在第一和第二应力膜上的层间绝缘膜。半导体器件还包括多个通过层间绝缘膜形成的第一接触孔和第一晶体管区域中的第一应力膜，以暴露第一栅极电极和第一源极/漏极区域，形成多个第二接触孔层间绝缘膜和第二晶体管区域中的第二应力膜，以暴露第二栅电极和第二源极/漏极区，以及通过层间绝缘膜，第二应力膜和第一应力膜形成的第三接触孔暴露第三栅电极的界面区域。形成第三接触孔的第三栅电极的上侧的凹部的深度等于或大于第一栅电极的上侧的凹部的深度，其中第一接触孔形成了。

9. 发明申请

US20070059923A1 Methods of fabricating damascene interconnection line in semiconductor devices and semiconductor devices fabricated using such methods 审中-公开
标题翻译：在使用这种方法制造的半导体器件和半导体器件中制造镶嵌互连线的方法
公开(公告)号：US20070059923A1
公开(公告)日：2007-03-15
申请号：US11445458
申请日：2006-06-02
申请人： Hyo-jong Lee , Ui-hyoung Lee , Hong-jae Shin , Nae-in Lee , Soo-geun Lee
发明人： Hyo-jong Lee , Ui-hyoung Lee , Hong-jae Shin , Nae-in Lee , Soo-geun Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/76802 , H01L21/76834 , H01L21/76843
摘要： Methods of fabricating an interconnection line in a semiconductor device and a semiconductor device including such an interconnection line. The method involves forming a lower interconnection line on a semiconductor substrate, forming a mold pattern that defines an opening through which the lower interconnection line is exposed, filling the opening with a conductive material to form a via, removing the mold pattern to make the via remain on the lower interconnection line, forming an interlevel dielectric (ILD) layer that covers the lower interconnection line and the via, patterning the ILD layer, exposing the via, forming a trench that defines a region in which an interconnection line is to be formed, and filling the trench to fabricate a damascene interconnection line connected to the via.
摘要翻译：在半导体器件中制造互连线的方法和包括这种互连线的半导体器件。该方法包括在半导体衬底上形成下部互连线，形成限定下部互连线暴露的开口的模具图案，用导电材料填充开口以形成通孔，去除模具图案以形成通孔保持在下互连线上，形成覆盖下互连线和通孔的层间电介质（ILD）层，图案化ILD层，暴露通孔，形成限定要形成互连线的区域的沟槽，并填充沟槽以制造连接到通孔的镶嵌互连线。

10. 发明申请

US20070117297A1 CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same 有权
标题翻译：具有埋入硅锗层的CMOS集成电路器件和衬底及其形成方法
公开(公告)号：US20070117297A1
公开(公告)日：2007-05-24
申请号：US11656717
申请日：2007-01-23
申请人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
发明人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
IPC分类号： H01L21/8234
CPC分类号： H01L29/66916 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66742 , H01L29/78609 , H01L29/78612 , H01L29/78621 , H01L29/78687 , H01L29/802
摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小峰值电平朝向未应变硅活性层的表面。峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

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