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1. 发明申请

US20110318533A1 METHOD OF DUPLICATING TEXTURE PATTERN ON OBJECT'S SURFACE BY NANO IMPRINTING AND ELECTROFORMING AND PATTERNED DUPLICATION PANEL USING THE SAME 审中-公开
标题翻译：使用NANO印刷和电镀和图案化复印面板将对象表面纹理图案复原的方法
公开(公告)号：US20110318533A1
公开(公告)日：2011-12-29
申请号：US13226631
申请日：2011-09-07
申请人： Kyung Wook LEE , Kyung Yul LEE , Jun Sang JEONG , Soo Han KIM
发明人： Kyung Wook LEE , Kyung Yul LEE , Jun Sang JEONG , Soo Han KIM
IPC分类号： B32B3/00 , B29C33/42 , B29C33/38 , C25D1/10
CPC分类号： B29C33/3857 , B44F9/00 , Y10T428/24355
摘要： Provided is a method of duplicating a nano-pattern texture of the surface of an object through electroforming using an imprint mold, including selecting the object having the surface texture to be duplicated; disposing the selected object and pre-treating the surface thereof; nano-imprinting the surface of the pretreated object, thus duplicating it on a plastic mold; metalizing the surface of the plastic mold through vapor deposition, and performing electroforming, thus manufacturing metal module master molds; trimming the edges of the metal module master molds, performing micro-processing, connecting the metal module master molds, and then performing electroforming, thus manufacturing a large-area metal unit master mold; and electroforming the metal unit master mold, thus producing a duplicate having the surface texture, thus exhibiting an effect in which the skin of a selected natural object can be duplicated on metal having a uniform thickness.
摘要翻译：提供了一种通过使用压印模具通过电铸来复制物体表面的纳米图案纹理的方法，包括选择具有待复制的表面纹理的物体; 布置所选择的物体并对其表面进行预处理; 纳米压印预处理物体的表面，从而将其复制在塑料模具上; 通过气相沉积对塑料模具的表面进行金属化，并进行电铸，从而制造金属模具主模具; 修剪金属模具主模具的边缘，执行微处理，连接金属模具主模具，然后执行电铸，从而制造大面积金属单元主模具; 并且电铸金属单元母模，从而产生具有表面纹理的副本，从而表现出一种效果，其中所选择的天然物体的皮肤可以复制在具有均匀厚度的金属上。

2. 发明申请

US20050230676A1 Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and devices so formed 失效
标题翻译：形成CMOS集成电路器件和其中具有掩埋硅锗层的衬底的方法以及如此形成的器件
公开(公告)号：US20050230676A1
公开(公告)日：2005-10-20
申请号：US11141275
申请日：2005-06-01
申请人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
发明人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
IPC分类号： H01L21/336 , H01L21/337 , H01L21/762 , H01L27/12 , H01L29/10 , H01L29/786 , H01L29/80 , H01L29/06
CPC分类号： H01L29/66916 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66742 , H01L29/78609 , H01L29/78612 , H01L29/78621 , H01L29/78687 , H01L29/802
摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小峰值电平朝向未应变硅活性层的表面。峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

3. 发明授权

US06914301B2 CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same 有权
标题翻译：具有掩埋硅锗层的CMOS集成电路器件和衬底及其形成方法
公开(公告)号：US06914301B2
公开(公告)日：2005-07-05
申请号：US10685116
申请日：2003-10-14
申请人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
发明人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
IPC分类号： H01L21/336 , H01L21/337 , H01L21/762 , H01L27/12 , H01L29/10 , H01L29/786 , H01L29/80 , H01L27/01
CPC分类号： H01L29/66916 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66742 , H01L29/78609 , H01L29/78612 , H01L29/78621 , H01L29/78687 , H01L29/802
摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小峰值电平朝向未应变硅活性层的表面。峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

4. 发明申请

US20100101961A1 Method of duplicating nano pattern texture on object's surface by nano imprinting and electroforming 审中-公开
标题翻译：通过纳米压印和电铸在物体表面上复制纳米图案纹理的方法
公开(公告)号：US20100101961A1
公开(公告)日：2010-04-29
申请号：US12655030
申请日：2009-12-22
申请人： Kyung Wook Lee , Kyung Yul Lee , Jun Sang Jeong
发明人： Kyung Wook Lee , Kyung Yul Lee , Jun Sang Jeong
IPC分类号： B41N1/04 , C25D1/00
CPC分类号： C25D1/10 , B23P15/24 , B29C33/3857 , C23C18/1657 , C25D1/006
摘要： Disclosed is a method of duplicating a nano-pattern texture of the surface of an object through electroforming using an imprint mold, including selecting the object having the surface texture to be duplicated; disposing the selected object and pre-treating the surface thereof; nano-imprinting the surface of the pretreated object, thus duplicating it on a plastic mold; metallizing the surface of the plastic mold through vapor deposition, and performing electroforming, thus manufacturing metal module master molds; trimming the edges of the metal module master molds, performing micro-processing, connecting the metal module master molds, and then performing electroforming, thus manufacturing a large-area metal unit master mold; and electroforming the metal unit master mold, thus producing a duplicate having the surface texture, thus exhibiting an effect in which the skin of a selected natural object can be duplicated on metal having a uniform thickness.
摘要翻译：公开了一种通过使用压印模具通过电铸来复制物体表面的纳米图案纹理的方法，包括选择具有待复制的表面纹理的物体; 布置所选择的物体并对其表面进行预处理; 纳米压印预处理物体的表面，从而将其复制在塑料模具上; 通过气相沉积对塑料模具的表面进行金属化，并执行电铸，从而制造金属模具主模具; 修剪金属模具主模具的边缘，执行微处理，连接金属模具主模具，然后执行电铸，从而制造大面积金属单元主模具; 并且电铸金属单元母模，从而产生具有表面纹理的副本，从而表现出一种效果，其中所选择的天然物体的皮肤可以复制在具有均匀厚度的金属上。

5. 发明授权

US07195987B2 Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein 有权
标题翻译：在其中形成CMOS集成电路器件和其中具有掩埋硅锗层的衬底的方法
公开(公告)号：US07195987B2
公开(公告)日：2007-03-27
申请号：US11141275
申请日：2005-05-31
申请人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
发明人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
IPC分类号： H01L21/76
CPC分类号： H01L29/66916 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66742 , H01L29/78609 , H01L29/78612 , H01L29/78621 , H01L29/78687 , H01L29/802
摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小峰值电平朝向未应变硅活性层的表面。峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

6. 发明授权

US06633066B1 CMOS integrated circuit devices and substrates having unstrained silicon active layers 失效
标题翻译： CMOS集成电路器件和具有非限制性硅有源层的衬底
公开(公告)号：US06633066B1
公开(公告)日：2003-10-14
申请号：US09711706
申请日：2000-11-13
申请人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
发明人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
IPC分类号： H01L310392
CPC分类号： H01L29/66916 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66742 , H01L29/78609 , H01L29/78612 , H01L29/78621 , H01L29/78687 , H01L29/802
摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1−xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1−xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peal Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1−xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1−xGex layer varies from the peak level where 0.2
摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。绝缘栅电极也设置在未应变硅有源层的表面上。还可以在电绝缘层和未应变硅活性层之间设置Si 1-x Ge x 层。 Si 1-x Ge x 层与未应变硅活性层形成第一结，并具有梯度浓度 Ge在从峰值电平向未应变硅有源层的表面延伸的第一方向上单调减小。 Peal Ge浓度水平大于x = 0.15，并且Si 1-x Ge x 层在峰值电平变化到在第一结处小于约x = 0.1的电平。 Ge在第一结处的浓度可能是突然的。更优选的是，Si >
层中的Ge的浓度， x <0.4到第一结处x = 0的水平。相对于表面，Si 1-x Ge x 层也具有退化的砷掺杂特性。 >

7. 发明授权

US5665631A SOI substrate manufacturing method 失效
标题翻译： SOI衬底制造方法
公开(公告)号：US5665631A
公开(公告)日：1997-09-09
申请号：US563803
申请日：1995-11-28
申请人： Byoung-hun Lee , Chi-jung Kang , Kyung-wook Lee , Gi-ho Cha
发明人： Byoung-hun Lee , Chi-jung Kang , Kyung-wook Lee , Gi-ho Cha
IPC分类号： H01L21/304 , H01L21/02 , H01L21/18 , H01L21/20 , H01L27/12 , H01L21/76
CPC分类号： H01L21/76256 , Y10S438/938
摘要： A SOI substrate manufacturing method which corrects the warpage in the SOI substrate by varying the thickness of a semiconductor material layer additionally formed over the bonded combination of a semiconductor substrate and supporting substrate.
摘要翻译：一种SOI衬底制造方法，其通过改变在半导体衬底和支撑衬底的接合组合上附加形成的半导体材料层的厚度来校正SOI衬底中的翘曲。

8. 发明申请

US20070117297A1 CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same 有权
标题翻译：具有埋入硅锗层的CMOS集成电路器件和衬底及其形成方法
公开(公告)号：US20070117297A1
公开(公告)日：2007-05-24
申请号：US11656717
申请日：2007-01-23
申请人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
发明人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
IPC分类号： H01L21/8234
CPC分类号： H01L29/66916 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66742 , H01L29/78609 , H01L29/78612 , H01L29/78621 , H01L29/78687 , H01L29/802
摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小峰值电平朝向未应变硅活性层的表面。峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

9. 发明授权

US5746883A Apparatus for bonding semiconductor wafers 失效
标题翻译：用于接合半导体晶片的装置
公开(公告)号：US5746883A
公开(公告)日：1998-05-05
申请号：US723239
申请日：1996-09-27
申请人： Gi-ho Cha , Chi-jung Kang , Byung-hun Lee , Kyung-wook Lee
发明人： Gi-ho Cha , Chi-jung Kang , Byung-hun Lee , Kyung-wook Lee
IPC分类号： H01L21/02 , H01L21/00 , B32B31/00
CPC分类号： H01L21/67132
摘要： An apparatus for bonding semiconductor wafers firmly bonds the wafers to each other and can always lay the bonded wafers on a desired bonding plate. The bonding plates have a plurality of grooves formed on their respective surfaces to reduce the bond force between the wafers and the bonding plates of the apparatus, and to prevent the wafers from sliding off the plates due to an air cushion. An interval controlling pin projects from the surface of one of the bonding plates to reduce breakage of the wafers by maintaining an interval between the bonding plates as they are are rotated towards each other. An elastic pad portion is installed on one the bonding plates for providing an elastic force for the wafers placed on the bonding plates so that the wafers bond to each other properly when the bonding plates are further rotated towards each other.
摘要翻译：用于接合半导体晶片的装置将晶片彼此牢固地结合，并且可以总是将结合的晶片放置在期望的接合板上。接合板在它们各自的表面上形成有多个槽，以减少晶片和设备的接合板之间的结合力，并且防止晶片由于气垫而从板上脱落。间隔控制销从一个接合板的表面突出，以通过在接合板之间彼此相对旋转时保持间隔而减小晶片的断裂。弹性垫部分安装在一个粘合板上，用于为粘合板上放置的晶片提供弹性力，使得当粘结板进一步相互转动时，晶片彼此粘合。

10. 发明授权

US09052425B2 Silicon solar cell 有权
标题翻译：硅太阳能电池
公开(公告)号：US09052425B2
公开(公告)日：2015-06-09
申请号：US13305059
申请日：2011-11-28
申请人： Kyung-Wook Lee , Kyung-Yul Lee , Bong-Yul Lee , Wayne H. Choe
发明人： Kyung-Wook Lee , Kyung-Yul Lee , Bong-Yul Lee , Wayne H. Choe
IPC分类号： G02B6/00 , G02B1/00 , G02B5/22 , G02B5/26 , H01L31/0687 , H01L31/043 , H01L31/056
CPC分类号： G02B1/005 , G02B5/22 , G02B5/26 , H01L31/043 , H01L31/056 , H01L31/0687 , Y02E10/52 , Y02E10/544 , Y02P70/521
摘要： A silicon solar cell is provided, including a first silicon layer that absorbing sunlight, a first layer of a structure of photonic crystals formed on the first silicon layer, and a second silicon layer formed on the first layer of a structure of photonic crystals and absorbing sunlight, wherein the first silicon layer and the second silicon layer absorb sunlight at different wavelengths and the first layer of structure of photonic crystals selectively reflects light of a wavelength absorbed by the second silicon layer.
摘要翻译：提供了一种硅太阳能电池，其包括吸收太阳光的第一硅层，形成在第一硅层上的光子晶体结构的第一层，以及形成在光子晶体结构的第一层上并吸收的第二硅层阳光，其中第一硅层和第二硅层吸收不同波长的太阳光，并且光子晶体的第一层结构选择性地反射由第二硅层吸收的波长的光。

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