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1. 发明授权

US06269051B1 Semiconductor device and timing control circuit 有权
公开(公告)号：US06269051B1
公开(公告)日：2001-07-31
申请号：US09640670
申请日：2000-08-18
申请人： Seiji Funaba , Yoji Nishio , Yuichi Okuda , Yoshinobu Nakagome
发明人： Seiji Funaba , Yoji Nishio , Yuichi Okuda , Yoshinobu Nakagome
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals.

2. 发明授权

US06212127B1 Semiconductor device and timing control circuit 有权
标题翻译：半导体器件和定时控制电路
公开(公告)号：US06212127B1
公开(公告)日：2001-04-03
申请号：US09563160
申请日：2000-05-01
申请人： Seiji Funaba , Yoji Nishio , Yuichi Okuda , Yoshinobu Nakagome
发明人： Seiji Funaba , Yoji Nishio , Yuichi Okuda , Yoshinobu Nakagome
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals.
摘要翻译：执行从可变延迟电路的输出到其延迟控制输入的延迟环路的操作速度。例如，分频电路分别置于可变延迟电路的输入和输出端。通过对从可变延迟电路输出的信号进行分频而获得的信号通过虚拟延迟电路被提供给相位比较器的一个输入，并且通过对可变延迟电路的输入进行分频而获得的信号被提供给另一个输入相位比较器。根据两个信号的相位之间的比较结果进行相位控制。

3. 再颁专利

USRE40205E1 Semiconductor device and timing control circuit 有权
标题翻译：半导体器件和定时控制电路
公开(公告)号：USRE40205E1
公开(公告)日：2008-04-01
申请号：US10226019
申请日：2002-08-23
申请人： Seiji Funaba , Yoji Nishio , Yuichi Okuda , Yoshinobu Nakagome
发明人： Seiji Funaba , Yoji Nishio , Yuichi Okuda , Yoshinobu Nakagome
IPC分类号： G11C11/4076
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals. Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals.
摘要翻译： <？delete-start id =“DEL-S-00001”date =“20080401”？从可变延迟电路的输出到延迟控制输入的延迟环路的操作速度进行控制。例如，分频电路分别置于可变延迟电路的输入和输出端。通过对从可变延迟电路输出的信号进行分频而获得的信号通过虚拟延迟电路被提供给相位比较器的一个输入，并且通过对可变延迟电路的输入进行分频而获得的信号被提供给另一个输入相位比较器。根据两个信号的相位比较结果执行相位控制。<？delete-end id =“DEL-S-00001”？> <？insert-start id =“INS-S-00001”date = 执行从可变延迟电路的输出到其延迟控制输入的延迟环的操作速度的控制。例如，分频电路分别置于可变延迟电路的输入和输出端。通过对从可变延迟电路输出的信号进行分频而获得的信号通过虚拟延迟电路被提供给相位比较器的一个输入，并且通过对可变延迟电路的输入进行分频而获得的信号被提供给另一个输入相位比较器。根据两个信号的相位之间的比较结果执行相位控制。<？insert-end id =“INS-S-00001”？>

4. 发明授权

US07936621B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07936621B2
公开(公告)日：2011-05-03
申请号：US12577365
申请日：2009-10-12
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： G11C7/00
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
摘要翻译：一种时钟发生电路，用于通过将通过可变延迟电路延迟通过外部端子输入的输入时钟信号与通过相位比较器电路的输入时钟信号相比较而获得的信号进行比较，从而控制延迟时间的可变延迟电路，其中时钟发生电路和由其形成的时钟信号操作的内部电路形成在公共半导体衬底上，其中元件形成区域形成时钟的电路与元件形成区电气隔离，其中数字电路依赖元件隔离技术构成在半导体衬底上。电源通道也与其他数字电路无关地形成。

5. 发明授权

US07411805B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07411805B2
公开(公告)日：2008-08-12
申请号：US11298514
申请日：2005-12-12
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： G11C5/06
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
摘要翻译：一种时钟发生电路，用于通过将通过可变延迟电路延迟通过外部端子输入的输入时钟信号与通过相位比较器电路的输入时钟信号相比较而获得的信号进行比较，从而控制延迟时间的可变延迟电路，其中时钟发生电路和由其形成的时钟信号操作的内部电路形成在公共半导体衬底上，其中元件形成区域形成时钟的电路与元件形成区电气隔离，其中数字电路依赖元件隔离技术构成在半导体衬底上。电源通道也与其他数字电路无关地形成。

6. 发明申请

US20050052944A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20050052944A1
公开(公告)日：2005-03-10
申请号：US10965845
申请日：2004-10-18
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/4074 , G11C11/4076 , H01L21/76 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H03K5/13 , H03K5/131 , H03L7/00 , H03L7/081 , H03L7/089 , H03L7/107 , G11C8/00
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
摘要翻译：一种时钟发生电路，用于通过将通过可变延迟电路延迟通过外部端子输入的输入时钟信号与通过相位比较器电路的输入时钟信号相比较而获得的信号进行比较，从而控制延迟时间的可变延迟电路，其中时钟发生电路和由其形成的时钟信号操作的内部电路形成在公共半导体衬底上，其中元件形成区域形成时钟的电路与元件形成区电气隔离，其中数字电路依赖元件隔离技术构成在半导体衬底上。电源通道也与其他数字电路无关地形成。

7. 发明申请

US20060087909A1 Semiconductor integrated circuit device 有权
公开(公告)号：US20060087909A1
公开(公告)日：2006-04-27
申请号：US11298514
申请日：2005-12-12
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： G11C8/00
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

8. 发明授权

US06819626B2 Semiconductor integrated circuit device 失效
公开(公告)号：US06819626B2
公开(公告)日：2004-11-16
申请号：US10614242
申请日：2003-07-08
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： G11C1100
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

9. 发明授权

US08179733B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08179733B2
公开(公告)日：2012-05-15
申请号：US13080958
申请日：2011-04-06
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： G11C7/00
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
摘要翻译：一种时钟发生电路，用于通过将通过可变延迟电路延迟通过外部端子输入的输入时钟信号与通过相位比较器电路的输入时钟信号相比较而获得的信号进行比较，从而控制延迟时间的可变延迟电路，其中时钟发生电路和由其形成的时钟信号操作的内部电路形成在公共半导体衬底上，其中元件形成区域形成时钟的电路与元件形成区电气隔离，其中数字电路依赖元件隔离技术构成在半导体衬底上。电源通道也与其他数字电路无关地形成。

10. 发明授权

US07602665B2 Semiconductor integrated circuit device 失效
公开(公告)号：US07602665B2
公开(公告)日：2009-10-13
申请号：US12169253
申请日：2008-07-08
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： G11C5/14
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

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