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1. 发明授权

US06656790B2 Method for manufacturing a semiconductor device including storage nodes of capacitor 有权
标题翻译：用于制造包括电容器的存储节点的半导体器件的方法
公开(公告)号：US06656790B2
公开(公告)日：2003-12-02
申请号：US10078885
申请日：2002-02-19
申请人： Se-myeong Jang , Ki-nam Kim , Hong-sik Jeong , Yoo-sang Hwang
发明人： Se-myeong Jang , Ki-nam Kim , Hong-sik Jeong , Yoo-sang Hwang
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L21/76895 , H01L21/76897 , H01L27/10814 , H01L28/91
摘要： A semiconductor device including storage nodes of a capacitor and a method for manufacturing the same are provided. Bit lines are formed on a semiconductor substrate, and protection layers are formed to cover and protect the bit lines. Conductive contact pads are formed between the bit lines and are level with the top surfaces of the protection layers. A node supporting layer is formed to cover the conductive contact pads and the protection layers. An etching stopper is formed on the node supporting layer. The mold layer, the etching stopper, and the node supporting layer are patterned, thereby forming opening holes exposing the conductive pads. Storage nodes are formed in the opening holes and have the shape of the profile of the opening holes. The mold layer exposed by the storage nodes is removed, thereby exposing the outer wall of each of the storage nodes positioned above the etching stopper.
摘要翻译：提供了包括电容器的存储节点的半导体器件及其制造方法。位线形成在半导体衬底上，形成保护层以覆盖并保护位线。导电接触焊盘形成在位线之间并与保护层的顶表面平齐。形成节点支撑层以覆盖导电接触焊盘和保护层。在节点支撑层上形成蚀刻止挡件。模塑层，蚀刻阻挡层和节点支撑层被图案化，从而形成露出导电焊盘的开孔。存储节点形成在开孔中并且具有开孔的轮廓的形状。由存储节点露出的模具层被去除，从而暴露位于蚀刻停止器上方的每个存储节点的外壁。

2. 发明授权

US08293644B2 Methods of manufacturing a semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US08293644B2
公开(公告)日：2012-10-23
申请号：US12656969
申请日：2010-02-22
申请人： Se-myeong Jang , Min-sung Kang
发明人： Se-myeong Jang , Min-sung Kang
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76804 , H01L21/76814 , H01L21/76897 , H01L23/485 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer.
摘要翻译：形成半导体的方法包括在其中限定了第一区域和第二区域的半导体衬底上形成绝缘层。通过绝缘层的存储节点接触（SNC）形成并电连接到第一区域。沉积穿过绝缘层的导电层并与绝缘层和SNC上的第二区电连接。通过去除导电层的上部，绝缘层的上部和SNC的上部形成位线，直到SNC和导电层彼此电分离，其中位线是剩余的导电层的一部分。

3. 发明申请

US20080001235A1 Integrated Circuit Devices Having Uniform Silicide Junctions 有权
标题翻译：具有均匀硅化物结合的集成电路器件
公开(公告)号：US20080001235A1
公开(公告)日：2008-01-03
申请号：US11853361
申请日：2007-09-11
申请人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
发明人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
IPC分类号： H01L29/78
CPC分类号： H01L29/41783 , H01L21/28247 , H01L21/28518 , H01L21/823418 , H01L27/105 , H01L27/10873 , H01L27/10894 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.
摘要翻译：提供集成电路器件，其包括集成电路衬底和集成电路衬底上的栅极。门有侧壁。阻挡层间隔件设置在栅极的侧壁上。阻挡层间隔物的一部分从栅极的侧壁突出，暴露出面向集成电路基板的阻挡层隔离物的下表面。在从栅极的侧壁突出的阻挡层隔离物的部分上提供硅化物层。

4. 发明授权

US06974752B2 Methods of fabricating integrated circuit devices having uniform silicide junctions 有权
标题翻译：制造具有均匀硅化物结的集成电路器件的方法
公开(公告)号：US06974752B2
公开(公告)日：2005-12-13
申请号：US10422430
申请日：2003-04-24
申请人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
发明人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/417 , H01L29/78
CPC分类号： H01L29/41783 , H01L21/28247 , H01L21/28518 , H01L21/823418 , H01L27/105 , H01L27/10873 , H01L27/10894 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： A gate having sidewalls is formed on an integrated circuit substrate. A barrier layer spacer is formed on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is formed on the portion of the barrier layer spacer protruding from the sidewalls of the gate. Related devices are also provided.
摘要翻译：具有侧壁的栅极形成在集成电路基板上。在栅极的侧壁上形成阻挡层间隔物。阻挡层间隔物的一部分从栅极的侧壁突出，暴露出面向集成电路基板的阻挡层隔离物的下表面。在从栅极的侧壁突出的阻挡层隔离物的部分上形成硅化物层。还提供了相关设备。

5. 发明授权

US07803684B2 Method of fabricating semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer 有权
标题翻译：具有通过选择性外延生长（SEG）层延伸的结的半导体器件的制造方法
公开(公告)号：US07803684B2
公开(公告)日：2010-09-28
申请号：US12585588
申请日：2009-09-18
申请人： Se-myeong Jang , Woun-suck Yang , Jae-man Yoon , Hyun-ju Sung
发明人： Se-myeong Jang , Woun-suck Yang , Jae-man Yoon , Hyun-ju Sung
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02631 , H01L21/02639 , H01L29/165 , H01L29/66636 , H01L29/66818 , H01L29/7854
摘要： In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion.
摘要翻译：在半导体器件及其制造方法中，半导体器件包括从衬底延伸的突起和围绕突起的上部的选择性外延生长（SEG）层，SEG层暴露出沟道区的侧壁突起。

6. 发明授权

US07737512B2 Integrated circuit devices having uniform silicide junctions 有权
标题翻译：具有均匀硅化物结的集成电路器件
公开(公告)号：US07737512B2
公开(公告)日：2010-06-15
申请号：US11853361
申请日：2007-09-11
申请人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
发明人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
IPC分类号： H01L31/119
CPC分类号： H01L29/41783 , H01L21/28247 , H01L21/28518 , H01L21/823418 , H01L27/105 , H01L27/10873 , H01L27/10894 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.
摘要翻译：提供集成电路器件，其包括集成电路衬底和集成电路衬底上的栅极。门有侧壁。阻挡层间隔件设置在栅极的侧壁上。阻挡层间隔物的一部分从栅极的侧壁突出，暴露出面向集成电路基板的阻挡层隔离物的下表面。在从栅极的侧壁突出的阻挡层隔离物的部分上提供硅化物层。

7. 发明授权

US07329927B2 Integrated circuit devices having uniform silicide junctions 有权
标题翻译：具有均匀硅化物结的集成电路器件
公开(公告)号：US07329927B2
公开(公告)日：2008-02-12
申请号：US11166979
申请日：2005-06-24
申请人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
发明人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
IPC分类号： H01L31/119
CPC分类号： H01L29/41783 , H01L21/28247 , H01L21/28518 , H01L21/823418 , H01L27/105 , H01L27/10873 , H01L27/10894 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.
摘要翻译：提供集成电路器件，其包括集成电路衬底和集成电路衬底上的栅极。门有侧壁。阻挡层间隔件设置在栅极的侧壁上。阻挡层间隔物的一部分从栅极的侧壁突出，暴露出面向集成电路基板的阻挡层隔离物的下表面。在从栅极的侧壁突出的阻挡层隔离物的部分上提供硅化物层。

8. 发明申请

US20060049455A1 Semiconductor devices with local recess channel transistors and methods of manufacturing the same 有权
标题翻译：具有局部凹槽沟道晶体管的半导体器件及其制造方法
公开(公告)号：US20060049455A1
公开(公告)日：2006-03-09
申请号：US11211378
申请日：2005-08-25
申请人： Se-myeong Jang , Yong-chul Oh , Makoto Yoshida
发明人： Se-myeong Jang , Yong-chul Oh , Makoto Yoshida
IPC分类号： H01L29/94
CPC分类号： H01L29/4236 , H01L29/66537 , H01L29/66553 , H01L29/66621 , H01L29/7834
摘要： A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded. A gate insulating layer is formed on the substrate in the recess trench. A gate electrode layer is formed on the gate insulating layer in the recess trench. A portion of the gate insulating layer and the gate electrode layer is etched to form a gate.
摘要翻译：一种在半导体器件中制造局部凹槽沟道晶体管的方法。在暴露基板的一部分的半导体基板上形成硬掩模层。使用硬掩模层作为蚀刻掩模蚀刻衬底的暴露部分以形成凹陷沟槽。在衬底上沿凹槽的侧壁的一部分形成沟槽隔离物。在形成沟槽间隔物之后，沿着凹槽的下部的衬底露出。沿着凹槽的下部的衬底的暴露部分被掺杂沟道杂质以形成围绕凹槽的下部的局部沟道杂质掺杂区。在凹槽的下部周围的局部沟道杂质掺杂区域的一部分掺杂有第V +调节杂质，以形成第五调制杂质掺杂区域内的第V + 局部沟道杂质掺杂区。凹槽的下部的宽度被扩大。在凹槽中的基板上形成栅极绝缘层。在凹槽中的栅极绝缘层上形成栅极电极层。栅极绝缘层和栅极电极层的一部分被蚀刻以形成栅极。

9. 发明授权

US07842572B2 Methods of manufacturing semiconductor devices with local recess channel transistors 有权
标题翻译：制造具有局部凹槽沟道晶体管的半导体器件的方法
公开(公告)号：US07842572B2
公开(公告)日：2010-11-30
申请号：US12534340
申请日：2009-08-03
申请人： Se-myeong Jang , Yong-chul Oh , Makoto Yoshida
发明人： Se-myeong Jang , Yong-chul Oh , Makoto Yoshida
IPC分类号： H01L21/336
CPC分类号： H01L29/4236 , H01L29/66537 , H01L29/66553 , H01L29/66621 , H01L29/7834
摘要： A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded. A gate insulating layer is formed on the substrate in the recess trench. A gate electrode layer is formed on the gate insulating layer in the recess trench. A portion of the gate insulating layer and the gate electrode layer is etched to form a gate.
摘要翻译：一种在半导体器件中制造局部凹槽沟道晶体管的方法。在暴露基板的一部分的半导体基板上形成硬掩模层。使用硬掩模层作为蚀刻掩模蚀刻衬底的暴露部分以形成凹陷沟槽。在衬底上沿凹槽的侧壁的一部分形成沟槽隔离物。在形成沟槽间隔物之后，沿着凹槽的下部的衬底露出。沿着凹槽的下部的衬底的暴露部分被掺杂沟道杂质以形成围绕凹槽的下部的局部沟道杂质掺杂区。在凹槽的下部周围的局部沟道杂质掺杂区域的一部分掺杂有Vth调整杂质，以在本地沟道杂质掺杂区域内部形成Vth调制杂质掺杂区域。凹槽的下部的宽度被扩大。在凹槽中的基板上形成栅极绝缘层。在凹槽中的栅极绝缘层上形成栅极电极层。栅极绝缘层和栅极电极层的一部分被蚀刻以形成栅极。

10. 发明授权

US07655988B2 Method of manufacturing multi-channel transistor device and multi-channel transistor device manufactured using the method 有权
标题翻译：使用该方法制造多通道晶体管器件和多通道晶体管器件的方法
公开(公告)号：US07655988B2
公开(公告)日：2010-02-02
申请号：US11241179
申请日：2005-09-30
申请人： Se-myeong Jang , Woun-suck Yang , Min-sang Kim
发明人： Se-myeong Jang , Woun-suck Yang , Min-sang Kim
IPC分类号： H01L27/088
CPC分类号： H01L29/7851 , H01L27/10876 , H01L27/10879 , H01L29/42392 , H01L29/66545 , H01L29/66818
摘要： A multi-channel transistor device and a method of manufacturing the same are provided. The method of a manufacturing a multi-channel transistor device includes defining an active region in a semiconductor substrate by forming an isolation layer exposing an upper side portion of the active region. An active expanding region is formed on the exposed upper side portion of the active region by selective epitaxial growth (SEG). A portion of the active region is selectively etched to define first channel bars in the active expanding region that extend between first and second laterally separated portions of the active region and a second channel bar that is an unetched portion of the active region. A portion of the isolation layer is selectively removed such as to expose side portions of the second channel bar and bottom surface portions of the first channel bars. A gate is formed on the first and second channel bars with a gate dielectric layer between the gate and the channel bars. A source/drain region is formed in a region of the active expanding region adjacent to the gate, thereby resulting in a multi-channel transistor structure.
摘要翻译：提供了多通道晶体管器件及其制造方法。制造多通道晶体管器件的方法包括通过形成暴露有源区的上侧部分的隔离层来限定半导体衬底中的有源区。通过选择性外延生长（SEG）在有源区的暴露的上侧部分上形成有源扩展区。有源区域的一部分被选择性地蚀刻以限定在有源扩展区域中的第一通道条，该有源扩展区域在有源区域的第一和第二横向分离部分之间延伸，而第二通道条是有源区的未蚀刻部分。选择性地去除隔离层的一部分，以暴露第二通道杆的侧部和第一通道杆的底表面部分。栅极形成在第一和第二沟道条上，栅极介电层和沟道条之间具有栅极电介质层。源极/漏极区域形成在与栅极相邻的有源扩展区域的区域中，从而形成多沟道晶体管结构。

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