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1. 发明授权

US07803684B2 Method of fabricating semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer 有权
标题翻译：具有通过选择性外延生长（SEG）层延伸的结的半导体器件的制造方法
公开(公告)号：US07803684B2
公开(公告)日：2010-09-28
申请号：US12585588
申请日：2009-09-18
申请人： Se-myeong Jang , Woun-suck Yang , Jae-man Yoon , Hyun-ju Sung
发明人： Se-myeong Jang , Woun-suck Yang , Jae-man Yoon , Hyun-ju Sung
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02631 , H01L21/02639 , H01L29/165 , H01L29/66636 , H01L29/66818 , H01L29/7854
摘要： In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion.
摘要翻译：在半导体器件及其制造方法中，半导体器件包括从衬底延伸的突起和围绕突起的上部的选择性外延生长（SEG）层，SEG层暴露出沟道区的侧壁突起。

2. 发明授权

US07592686B2 Semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer and method of fabricating the same 有权
标题翻译：具有通过选择性外延生长（SEG）层延伸的结的半导体器件及其制造方法
公开(公告)号：US07592686B2
公开(公告)日：2009-09-22
申请号：US11099603
申请日：2005-04-06
申请人： Se-myeong Jang , Woun-suck Yang , Jae-man Yoon , Hyun-ju Sung
发明人： Se-myeong Jang , Woun-suck Yang , Jae-man Yoon , Hyun-ju Sung
IPC分类号： H01L29/06
CPC分类号： H01L29/7851 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02631 , H01L21/02639 , H01L29/165 , H01L29/66636 , H01L29/66818 , H01L29/7854
摘要： In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion.
摘要翻译：在半导体器件及其制造方法中，半导体器件包括从衬底延伸的突起和围绕突起的上部的选择性外延生长（SEG）层，SEG层暴露出沟道区的侧壁突起。

3. 发明申请

US20100015768A1 Method of fabricating semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer 有权
公开(公告)号：US20100015768A1
公开(公告)日：2010-01-21
申请号：US12585588
申请日：2009-09-18
申请人： Se-myeong Jang , Woun-suck Yang , Jae-man Yoon , Hyun-ju Sung
发明人： Se-myeong Jang , Woun-suck Yang , Jae-man Yoon , Hyun-ju Sung
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02631 , H01L21/02639 , H01L29/165 , H01L29/66636 , H01L29/66818 , H01L29/7854
摘要： In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion.

4. 发明申请

US20060054969A1 Semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer and method of fabricating the same 有权
公开(公告)号：US20060054969A1
公开(公告)日：2006-03-16
申请号：US11099603
申请日：2005-04-06
申请人： Se-myeong Jang , Woun-suck Yang , Jae-man Yoon , Hyun-ju Sung
发明人： Se-myeong Jang , Woun-suck Yang , Jae-man Yoon , Hyun-ju Sung
IPC分类号： H01L29/76 , H01L21/20
CPC分类号： H01L29/7851 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02631 , H01L21/02639 , H01L29/165 , H01L29/66636 , H01L29/66818 , H01L29/7854
摘要： In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion.

5. 发明授权

US07655988B2 Method of manufacturing multi-channel transistor device and multi-channel transistor device manufactured using the method 有权
标题翻译：使用该方法制造多通道晶体管器件和多通道晶体管器件的方法
公开(公告)号：US07655988B2
公开(公告)日：2010-02-02
申请号：US11241179
申请日：2005-09-30
申请人： Se-myeong Jang , Woun-suck Yang , Min-sang Kim
发明人： Se-myeong Jang , Woun-suck Yang , Min-sang Kim
IPC分类号： H01L27/088
CPC分类号： H01L29/7851 , H01L27/10876 , H01L27/10879 , H01L29/42392 , H01L29/66545 , H01L29/66818
摘要： A multi-channel transistor device and a method of manufacturing the same are provided. The method of a manufacturing a multi-channel transistor device includes defining an active region in a semiconductor substrate by forming an isolation layer exposing an upper side portion of the active region. An active expanding region is formed on the exposed upper side portion of the active region by selective epitaxial growth (SEG). A portion of the active region is selectively etched to define first channel bars in the active expanding region that extend between first and second laterally separated portions of the active region and a second channel bar that is an unetched portion of the active region. A portion of the isolation layer is selectively removed such as to expose side portions of the second channel bar and bottom surface portions of the first channel bars. A gate is formed on the first and second channel bars with a gate dielectric layer between the gate and the channel bars. A source/drain region is formed in a region of the active expanding region adjacent to the gate, thereby resulting in a multi-channel transistor structure.
摘要翻译：提供了多通道晶体管器件及其制造方法。制造多通道晶体管器件的方法包括通过形成暴露有源区的上侧部分的隔离层来限定半导体衬底中的有源区。通过选择性外延生长（SEG）在有源区的暴露的上侧部分上形成有源扩展区。有源区域的一部分被选择性地蚀刻以限定在有源扩展区域中的第一通道条，该有源扩展区域在有源区域的第一和第二横向分离部分之间延伸，而第二通道条是有源区的未蚀刻部分。选择性地去除隔离层的一部分，以暴露第二通道杆的侧部和第一通道杆的底表面部分。栅极形成在第一和第二沟道条上，栅极介电层和沟道条之间具有栅极电介质层。源极/漏极区域形成在与栅极相邻的有源扩展区域的区域中，从而形成多沟道晶体管结构。

6. 发明申请

US20060073662A1 Method of manufacturing multi-channel transistor device and multi-channel transistor device manufactured using the method 有权
标题翻译：使用该方法制造多通道晶体管器件和多通道晶体管器件的方法
公开(公告)号：US20060073662A1
公开(公告)日：2006-04-06
申请号：US11241179
申请日：2005-09-30
申请人： Se-myeong Jang , Woun-suck Yang , Min-sang Kim
发明人： Se-myeong Jang , Woun-suck Yang , Min-sang Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L27/10876 , H01L27/10879 , H01L29/42392 , H01L29/66545 , H01L29/66818
摘要： A multi-channel transistor device and a method of manufacturing the same are provided. The method of a manufacturing a multi-channel transistor device includes defining an active region in a semiconductor substrate by forming an isolation layer exposing an upper side portion of the active region. An active expanding region is formed on the exposed upper side portion of the active region by selective epitaxial growth (SEG). A portion of the active region is selectively etched to define first channel bars in the active expanding region that extend between first and second laterally separated portions of the active region and a second channel bar that is an unetched portion of the active region. A portion of the isolation layer is selectively removed such as to expose side portions of the second channel bar and bottom surface portions of the first channel bars. A gate is formed on the first and second channel bars with a gate dielectric layer between the gate and the channel bars. A source/drain region is formed in a region of the active expanding region adjacent to the gate, thereby resulting in a multi-channel transistor structure.
摘要翻译：提供了多通道晶体管器件及其制造方法。制造多通道晶体管器件的方法包括通过形成暴露有源区的上侧部分的隔离层来限定半导体衬底中的有源区。通过选择性外延生长（SEG）在有源区的暴露的上侧部分上形成有源扩展区。有源区域的一部分被选择性地蚀刻以限定在有源扩展区域中的第一通道条，该有源扩展区域在有源区域的第一和第二横向分离部分之间延伸，而第二通道条是有源区的未蚀刻部分。选择性地去除隔离层的一部分，以暴露第二通道杆的侧部和第一通道杆的底表面部分。栅极形成在第一和第二沟道条上，栅极介电层和沟道条之间具有栅极电介质层。源极/漏极区域形成在与栅极相邻的有源扩展区域的区域中，从而形成多沟道晶体管结构。

7. 发明授权

US07935600B2 Method of manufacturing multi-channel transistor device and multi-channel transistor device manufactured using the method 有权
标题翻译：使用该方法制造多通道晶体管器件和多通道晶体管器件的方法
公开(公告)号：US07935600B2
公开(公告)日：2011-05-03
申请号：US12637114
申请日：2009-12-14
申请人： Se-myeong Jang , Woun-suck Yang , Min-sang Kim
发明人： Se-myeong Jang , Woun-suck Yang , Min-sang Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L27/10876 , H01L27/10879 , H01L29/42392 , H01L29/66545 , H01L29/66818
摘要： A multi-channel transistor device and a method of manufacturing the same are provided. The method of a manufacturing a multi-channel transistor device includes defining an active region in a semiconductor substrate by forming an isolation layer exposing an upper side portion of the active region. An active expanding region is formed on the exposed upper side portion of the active region by selective epitaxial growth (SEG). A portion of the active region is selectively etched to define first channel bars in the active expanding region that extend between first and second laterally separated portions of the active region and a second channel bar that is an unetched portion of the active region. A portion of the isolation layer is selectively removed such as to expose side portions of the second channel bar and bottom surface portions of the first channel bars. A gate is formed on the first and second channel bars with a gate dielectric layer between the gate and the channel bars. A source/drain region is formed in a region of the active expanding region adjacent to the gate, thereby resulting in a multi-channel transistor structure.
摘要翻译：提供了多通道晶体管器件及其制造方法。制造多通道晶体管器件的方法包括通过形成暴露有源区的上侧部分的隔离层来限定半导体衬底中的有源区。通过选择性外延生长（SEG）在有源区的暴露的上侧部分上形成有源扩展区。有源区域的一部分被选择性蚀刻以限定在有源扩展区域中的第一通道条，该有源扩展区域在有源区域的第一和第二横向分离部分之间延伸，而第二通道条是有源区的未蚀刻部分。选择性地去除隔离层的一部分，以暴露第二通道杆的侧部和第一通道杆的底表面部分。栅极形成在第一和第二沟道条上，栅极介电层和沟道条之间具有栅极电介质层。源极/漏极区域形成在与栅极相邻的有源扩展区域的区域中，从而形成多沟道晶体管结构。

8. 发明申请

US20100093146A1 METHOD OF MANUFACTURING MULTI-CHANNEL TRANSISTOR DEVICE AND MULTI-CHANNEL TRANSISTOR DEVICE MANUFACTURED USING THE METHOD 有权
标题翻译：制造多通道晶体管器件的方法和使用该方法制造的多通道晶体管器件
公开(公告)号：US20100093146A1
公开(公告)日：2010-04-15
申请号：US12637114
申请日：2009-12-14
申请人： Se-myeong Jang , Woun-suck Yang , Min-sang Kim
发明人： Se-myeong Jang , Woun-suck Yang , Min-sang Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L27/10876 , H01L27/10879 , H01L29/42392 , H01L29/66545 , H01L29/66818
摘要： A multi-channel transistor device and a method of manufacturing the same are provided. The method of a manufacturing a multi-channel transistor device includes defining an active region in a semiconductor substrate by forming an isolation layer exposing an upper side portion of the active region. An active expanding region is formed on the exposed upper side portion of the active region by selective epitaxial growth (SEG). A portion of the active region is selectively etched to define first channel bars in the active expanding region that extend between first and second laterally separated portions of the active region and a second channel bar that is an unetched portion of the active region. A portion of the isolation layer is selectively removed such as to expose side portions of the second channel bar and bottom surface portions of the first channel bars. A gate is formed on the first and second channel bars with a gate dielectric layer between the gate and the channel bars. A source/drain region is formed in a region of the active expanding region adjacent to the gate, thereby resulting in a multi-channel transistor structure.
摘要翻译：提供了多通道晶体管器件及其制造方法。制造多通道晶体管器件的方法包括通过形成暴露有源区的上侧部分的隔离层来限定半导体衬底中的有源区。通过选择性外延生长（SEG）在有源区的暴露的上侧部分上形成有源扩展区。有源区域的一部分被选择性地蚀刻以限定主动扩展区域中在有源区域的第一和第二横向分离部分之间延伸的第一通道条和作为有源区域的未蚀刻部分的第二通道条。选择性地去除隔离层的一部分，以暴露第二通道杆的侧部和第一通道杆的底表面部分。栅极形成在第一和第二沟道条上，栅极介电层和沟道条之间具有栅极电介质层。源极/漏极区域形成在与栅极相邻的有源扩展区域的区域中，从而形成多沟道晶体管结构。

9. 发明授权

US08293644B2 Methods of manufacturing a semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US08293644B2
公开(公告)日：2012-10-23
申请号：US12656969
申请日：2010-02-22
申请人： Se-myeong Jang , Min-sung Kang
发明人： Se-myeong Jang , Min-sung Kang
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76804 , H01L21/76814 , H01L21/76897 , H01L23/485 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer.
摘要翻译：形成半导体的方法包括在其中限定了第一区域和第二区域的半导体衬底上形成绝缘层。通过绝缘层的存储节点接触（SNC）形成并电连接到第一区域。沉积穿过绝缘层的导电层并与绝缘层和SNC上的第二区电连接。通过去除导电层的上部，绝缘层的上部和SNC的上部形成位线，直到SNC和导电层彼此电分离，其中位线是剩余的导电层的一部分。

10. 发明申请

US20080001235A1 Integrated Circuit Devices Having Uniform Silicide Junctions 有权
标题翻译：具有均匀硅化物结合的集成电路器件
公开(公告)号：US20080001235A1
公开(公告)日：2008-01-03
申请号：US11853361
申请日：2007-09-11
申请人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
发明人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
IPC分类号： H01L29/78
CPC分类号： H01L29/41783 , H01L21/28247 , H01L21/28518 , H01L21/823418 , H01L27/105 , H01L27/10873 , H01L27/10894 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.
摘要翻译：提供集成电路器件，其包括集成电路衬底和集成电路衬底上的栅极。门有侧壁。阻挡层间隔件设置在栅极的侧壁上。阻挡层间隔物的一部分从栅极的侧壁突出，暴露出面向集成电路基板的阻挡层隔离物的下表面。在从栅极的侧壁突出的阻挡层隔离物的部分上提供硅化物层。

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