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1. 发明授权

US09536822B2 Drawn dummy FeCAP, via and metal structures 有权
标题翻译：绘制虚拟FeCAP，通孔和金属结构
公开(公告)号：US09536822B2
公开(公告)日：2017-01-03
申请号：US12576340
申请日：2009-10-09
申请人： Scott R. Summerfelt , Rajni J. Aggarwal
发明人： Scott R. Summerfelt , Rajni J. Aggarwal
IPC分类号： H01L21/02 , H01L21/00 , H01L23/522 , H01L23/58 , H01L27/02 , H01L49/02 , H01L27/115
CPC分类号： H01L23/522 , H01L23/5223 , H01L23/585 , H01L27/0207 , H01L27/11507 , H01L28/55 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/00
摘要： An integrated circuit containing hydrogen permeable dummy vias configured in a linear or rectangular array and symmetrically positioned over a component in the integrated circuit. An integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components. A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.
摘要翻译：一种集成电路，其包含配置在线性或矩形阵列中并且对称地位于集成电路中的部件上的氢可渗透虚设通孔。包含具有相同布局的匹配部件和在匹配部件上具有相同配置的氢可渗透虚拟过孔的集成电路。形成集成电路的过程，该集成电路包含具有相同布局的匹配部件和在匹配部件上具有相同构造的氢可渗透虚设通孔。

2. 发明授权

US08377719B2 Drawn dummy FeCAP, via and metal structures 有权
标题翻译：绘制虚拟FeCAP，通孔和金属结构
公开(公告)号：US08377719B2
公开(公告)日：2013-02-19
申请号：US13307829
申请日：2011-11-30
申请人： Scott R. Summerfelt , Rajni J. Aggarwal
发明人： Scott R. Summerfelt , Rajni J. Aggarwal
IPC分类号： H01L21/00
CPC分类号： H01L23/522 , H01L23/5223 , H01L23/585 , H01L27/0207 , H01L27/11507 , H01L28/55 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/00
摘要： A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.
摘要翻译：形成集成电路的过程，该集成电路包含具有相同布局的匹配部件和在匹配部件上具有相同构造的氢可渗透虚设通孔。

3. 发明申请

US20120077287A1 DRAWN DUMMY FeCAP, VIA AND METAL STRUCTURES 有权
标题翻译：抽烟费，通风和金属结构
公开(公告)号：US20120077287A1
公开(公告)日：2012-03-29
申请号：US13307829
申请日：2011-11-30
申请人： Scott R. Summerfelt , Rajni J. Aggarwal
发明人： Scott R. Summerfelt , Rajni J. Aggarwal
IPC分类号： H01L21/02
CPC分类号： H01L23/522 , H01L23/5223 , H01L23/585 , H01L27/0207 , H01L27/11507 , H01L28/55 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/00
摘要： A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.
摘要翻译：形成集成电路的过程，该集成电路包含具有相同布局的匹配部件和在匹配部件上具有相同构造的氢可渗透虚设通孔。

4. 发明申请

US20110079878A1 FERROELECTRIC CAPACITOR ENCAPSULATED WITH A HYDROGEN BARRIER 审中-公开
标题翻译：用氢气隔离器封装的电磁电容器
公开(公告)号：US20110079878A1
公开(公告)日：2011-04-07
申请号：US12890219
申请日：2010-09-24
申请人： Rajni J. Aggarwal , Scott R. Summerfelt , Gul B. Basim , Ted S. Moise
发明人： Rajni J. Aggarwal , Scott R. Summerfelt , Gul B. Basim , Ted S. Moise
IPC分类号： H01L29/92 , H01L21/00
CPC分类号： H01L28/57 , H01L27/11507 , H01L27/11509 , H01L28/55
摘要： An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.
摘要翻译：包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路。一种用于形成包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路的方法。

5. 发明授权

US09773793B2 Transistor performance modification with stressor structures 有权
公开(公告)号：US09773793B2
公开(公告)日：2017-09-26
申请号：US12576310
申请日：2009-10-09
申请人： Scott R. Summerfelt , Rajni J. Aggarwal , Shaoping Tang
发明人： Scott R. Summerfelt , Rajni J. Aggarwal , Shaoping Tang
IPC分类号： H01L21/02 , H01L21/00 , H01L27/11507 , H01L49/02 , H01L29/78
CPC分类号： H01L27/11507 , H01L28/55 , H01L29/7833 , H01L29/7843
摘要： A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries.

6. 发明申请

US20110084323A1 Transistor Performance Modification with Stressor Structures 有权
标题翻译：晶体管性能改进与应力结构
公开(公告)号：US20110084323A1
公开(公告)日：2011-04-14
申请号：US12576310
申请日：2009-10-09
申请人： Scott R. Summerfelt , Rajni J. Aggarwal , Shaoping Tang
发明人： Scott R. Summerfelt , Rajni J. Aggarwal , Shaoping Tang
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/11507 , H01L28/55 , H01L29/7833 , H01L29/7843
摘要： A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries.
摘要翻译：具有应力增强几何形状的晶体管结构在通道区域上方对准。此外，具有应力增强几何形状的晶体管结构位于沟道区域的相对侧上方并与其对准。此外，制造含有具有应力增强几何形状的晶体管的集成电路的方法。

7. 发明申请

US20100090340A1 Drawn Dummy FeCAP, Via and Metal Structures 有权
标题翻译：绘制虚拟FeCAP，通孔和金属结构
公开(公告)号：US20100090340A1
公开(公告)日：2010-04-15
申请号：US12576340
申请日：2009-10-09
申请人： Scott R. Summerfelt , Rajni J. Aggarwal
发明人： Scott R. Summerfelt , Rajni J. Aggarwal
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/522 , H01L23/5223 , H01L23/585 , H01L27/0207 , H01L27/11507 , H01L28/55 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/00
摘要： An integrated circuit containing hydrogen permeable dummy vias configured in a linear or rectangular array and symmetrically positioned over a component in the integrated circuit. An integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components. A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.
摘要翻译：一种集成电路，其包含配置在线性或矩形阵列中并且对称地位于集成电路中的部件上的氢可渗透虚设通孔。包含具有相同布局的匹配部件和在匹配部件上具有相同配置的氢可渗透虚拟过孔的集成电路。形成集成电路的过程，该集成电路包含具有相同布局的匹配部件和在匹配部件上具有相同构造的氢可渗透虚设通孔。

8. 发明授权

US08779485B2 Hydrogen barrier for ferroelectric capacitors 有权
公开(公告)号：US08779485B2
公开(公告)日：2014-07-15
申请号：US13480044
申请日：2012-05-24
申请人： Kezhakkedath R. Udayakumar , Scott R. Summerfelt , Ted S. Moise , Manoj K. Jain
发明人： Kezhakkedath R. Udayakumar , Scott R. Summerfelt , Ted S. Moise , Manoj K. Jain
IPC分类号： H01L21/02 , H01L23/48 , H01L21/768 , H01L49/02 , H01L27/115
CPC分类号： H01L21/76843 , H01L27/11509 , H01L28/57
摘要： An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

9. 发明授权

US08416598B2 Differential plate line screen test for ferroelectric latch circuits 有权
公开(公告)号：US08416598B2
公开(公告)日：2013-04-09
申请号：US12781601
申请日：2010-05-17
申请人： Scott R. Summerfelt , John Anthony Rodriguez , Hugh P. McAdams , Steven Craig Bartling
发明人： Scott R. Summerfelt , John Anthony Rodriguez , Hugh P. McAdams , Steven Craig Bartling
IPC分类号： G11C11/22
CPC分类号： G11C29/50 , G11C11/22
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

10. 发明申请

US20120307545A1 Interleaved Bit Line Architecture for 2T2C Ferroelectric Memories 审中-公开
标题翻译： 2T2C铁电存储器的交错位线架构
公开(公告)号：US20120307545A1
公开(公告)日：2012-12-06
申请号：US13150885
申请日：2011-06-01
申请人： Hugh P. McAdams , Scott R. Summerfelt , Patrick M. Ndai
发明人： Hugh P. McAdams , Scott R. Summerfelt , Patrick M. Ndai
IPC分类号： G11C11/22
CPC分类号： G11C11/221
摘要： A ferroelectric memory with interleaved pairs of ferroelectric memory cells of the two-transistor, two-capacitor (2T2C) type. Each memory cell in a given pair is constructed as first and second portions, each portion including a transistor and a ferroelectric capacitor. Within each pair, a first portion of a second memory cell is physically located between the first and second portions of the first memory cell. As a result, complementary bit lines for adjacent columns are interleaved with one another. Each sense amplifier is associated with a multiplexer, so that the adjacent columns of the interleaved memory cells are supported by a single sense amplifier. Noise coupling among the bit lines is reduced, and the sense amplifiers can be placed along one side of the array, reducing the number of dummy cells required to eliminate edge cell effects.
摘要翻译：具有双晶体管，双电容器（2T2C）型的交错成对的铁电存储器单元的铁电存储器。给定对中的每个存储单元被构造为第一和第二部分，每个部分包括晶体管和铁电电容器。在每对内，第二存储单元的第一部分物理地位于第一存储单元的第一和第二部分之间。结果，用于相邻列的互补位线彼此交错。每个读出放大器与复用器相关联，使得交错存储器单元的相邻列由单个读出放大器支持。位线之间的噪声耦合减少，并且读出放大器可以沿着阵列的一侧放置，减少了消除边缘单元效应所需的虚拟单元的数量。

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