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1. 发明授权

US07607114B2 Designer's intent tolerance bands for proximity correction and checking 失效
标题翻译：设计师的意图容差带用于近距离校正和检查
公开(公告)号：US07607114B2
公开(公告)日：2009-10-20
申请号：US11778302
申请日：2007-07-16
申请人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
发明人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.
摘要翻译：通过为感兴趣的设计层形成公差带来提供设计者用于半导体设计的预期电气特性的方法，其考虑到与感兴趣的设计层上的特征相互作用并影响其特征的设计层的约束。该方法确定区域，即公差带，其中感兴趣层的特征的打印边缘将在预定标准内打印，并且满足各种约束，包括但不限于电气，重叠和可制造性约束特征对其他层的影响。该方法可以在用于在计算机系统上执行的计算机程序产品中实现。所得到的公差带可用于有效传达设计人员对平版印刷机，OPC工程师或掩模制造商或工具的意图。

2. 发明授权

US07266798B2 Designer's intent tolerance bands for proximity correction and checking 失效
标题翻译：设计师的意图容差带用于近距离校正和检查
公开(公告)号：US07266798B2
公开(公告)日：2007-09-04
申请号：US11163264
申请日：2005-10-12
申请人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
发明人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.
摘要翻译：通过为感兴趣的设计层形成公差带来提供设计者用于半导体设计的预期电气特性的方法，其考虑到与感兴趣的设计层上的特征相互作用并影响其特征的设计层的约束。该方法确定区域，即公差带，其中感兴趣层的特征的打印边缘将在预定标准内打印，并且满足各种约束，包括但不限于电气，重叠和可制造性约束特征对其他层的影响。该方法可以在用于在计算机系统上执行的计算机程序产品中实现。所得到的公差带可用于有效传达设计人员对平版印刷机，OPC工程师或掩模制造商或工具的意图。

3. 发明授权

US07650587B2 Local coloring for hierarchical OPC 失效
标题翻译：分层OPC的局部着色
公开(公告)号：US07650587B2
公开(公告)日：2010-01-19
申请号：US11564957
申请日：2006-11-30
申请人： Zachary Baum , Ioana Graur , Lars W. Liebmann , Scott M. Mansfield
发明人： Zachary Baum , Ioana Graur , Lars W. Liebmann , Scott M. Mansfield
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for designing a mask for fabricating an integrated circuit is provided wherein a mask layout that requires coloring, such as for alternating phase shift, double-exposure and double-exposure-etch masks, is organized into uncolored hierarchical design units. Prior to modification by OPC, each hierarchical design unit is locally colored. OPC is then performed on the locally colored hierarchical design unit. The local coloring information for the hierarchically arranged OPC-modified design unit may be discarded. After OPC modification, the uncolored OPC-modified design units may be placed within the mask layout, and the flattened data may be colored. Thus, turnaround time for mask design is significantly improved since the numerically intensive OPC is performed on the hierarchical data, avoiding the need to perform OPC on flattened data, whereas the less intensive global coloring is performed on flattened data.
摘要翻译：提供了一种用于设计用于制造集成电路的掩模的方法，其中需要诸如用于交替相移，双曝光和双曝光蚀刻掩模的着色的掩模布局被组织成无色层级设计单元。在OPC修改之前，每个分层设计单元都是局部有色的。然后在本地着色的分层设计单元上执行OPC。可以丢弃用于分层布置的OPC修改的设计单元的局部着色信息。在OPC修改之后，未着色的OPC修改的设计单元可以放置在掩模布局内，并且扁平化的数据可能被着色。因此，掩模设计的周转时间显着提高，因为对分层数据执行数字密集的OPC，避免了对平坦化数据执行OPC的需要，而对扁平化数据执行的密集型全局着色较少。

4. 发明申请

US20080127029A1 CLOSED-LOOP DESIGN FOR MANUFACTURABILITY PROCESS 失效
标题翻译：闭环设计用于制造工艺
公开(公告)号：US20080127029A1
公开(公告)日：2008-05-29
申请号：US11554904
申请日：2006-10-31
申请人： Ioana Graur , Geng Han , Scott M. Mansfield , Lars W. Liebmann
发明人： Ioana Graur , Geng Han , Scott M. Mansfield , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not be as accurate as the lithographic model used in preparing the lithographic mask layout during data prep. The resulting image contours are then included with the modified, optimized design layout to the data prep process, in which the mask layout is optimized using the lithographic process model, for example, including RET and OPC. The mask layout optimization matches the images simulated by the lithographic process model with the image contours generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout.
摘要翻译：提供一种设计集成电路的方法，其中使用过程模型优化设计布局，直到由过程模型模拟的图像轮廓满足设计约束。在设计阶段使用的过程模型不需要与在数据准备期间制备光刻掩模布局时使用的光刻模型一样精确。然后将所得到的图像轮廓与经修改的优化的设计布局一起包括在数据准备过程中，其中使用光刻过程模型（例如包括RET和OPC）优化掩模布局。掩模布局优化将由光刻过程模型模拟的图像与在设计阶段生成的图像轮廓相匹配，从而确保设计人员指定的设计和可制造性约束被优化的掩模布局所满足。

5. 发明申请

US20080134130A1 LOCAL COLORING FOR HIERARCHICAL OPC 失效
标题翻译：用于分层OPC的本地着色
公开(公告)号：US20080134130A1
公开(公告)日：2008-06-05
申请号：US11564957
申请日：2006-11-30
申请人： Zachary Baum , Ioana Graur , Lars W. Liebmann , Scott M. Mansfield
发明人： Zachary Baum , Ioana Graur , Lars W. Liebmann , Scott M. Mansfield
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for designing a mask for fabricating an integrated circuit is provided wherein a mask layout that requires coloring, such as for alternating phase shift, double-exposure and double-exposure-etch masks, is organized into uncolored hierarchical design units. Prior to modification by OPC, each hierarchical design unit is locally colored. OPC is then performed on the locally colored hierarchical design unit. The local coloring information for the hierarchically arranged OPC-modified design unit may be discarded. After OPC modification, the uncolored OPC-modified design units may be placed within the mask layout, and the flattened data may be colored. Thus, turnaround time for mask design is significantly improved since the numerically intensive OPC is performed on the hierarchical data, avoiding the need to perform OPC on flattened data, whereas the less intensive global coloring is performed on flattened data.
摘要翻译：提供了一种用于设计用于制造集成电路的掩模的方法，其中需要诸如用于交替相移，双曝光和双曝光蚀刻掩模的着色的掩模布局被组织成无色层级设计单元。在OPC修改之前，每个分层设计单元都是局部有色的。然后在本地着色的分层设计单元上执行OPC。可以丢弃用于分层布置的OPC修改的设计单元的局部着色信息。在OPC修改之后，未着色的OPC修改的设计单元可以放置在掩模布局内，并且扁平化的数据可能被着色。因此，掩模设计的周转时间显着提高，因为对分层数据执行数字密集型OPC，避免了对平坦化数据执行OPC的需要，而对扁平化数据执行的密集型全局着色较少。

6. 发明授权

US08174681B2 Calibration of lithographic process models 失效
标题翻译：光刻工艺模型的校准
公开(公告)号：US08174681B2
公开(公告)日：2012-05-08
申请号：US12349223
申请日：2009-01-06
申请人： Ioana Graur , Geng Han , Scott M. Mansfield , Michael Scaman
发明人： Ioana Graur , Geng Han , Scott M. Mansfield , Michael Scaman
IPC分类号： G03B27/32 , G01D18/00
CPC分类号： G03F7/70441 , G03F7/705
摘要： A method is provided for calibrating a model of a lithographic process that includes defining a parameter space of lithographic model parameters that are expected in an integrated circuit layout. The parameter space is defined according to bin values of a lithographic model parameter that span the range from a predetermined minimum and maximum value of the model parameter. The bin values may be incremented uniformly between the maximum and minimum parameter values, or may be distributed according to a weighting. The lithographic model is calibrated to an initial calibration test pattern. The resulting simulated calibration pattern is evaluated to determine whether the model parameter space is adequately populated. If the parameter space is over or under populated, the calibration pattern is modified until the calibration pattern test values adequately populate the parameter space, so that the final calibrated lithographic process model will more reliably predict images over the full range of image parameters.
摘要翻译：提供了一种用于校准光刻工艺的模型的方法，该方法包括定义在集成电路布局中期望的光刻模型参数的参数空间。参数空间根据距离模型参数的预定最小值和最大值的范围的光刻模型参数的二进制值定义。二进制值可以在最大和最小参数值之间均匀递增，也可以根据权重分配。光刻模型被校准为初始校准测试图案。评估所得到的模拟校准模式以确定模型参数空间是否被充分填充。如果参数空间超过或不足，校准模式将被修改，直到校准模式测试值充分填充参数空间，以便最终校准的光刻过程模型将在图像参数的全范围内更可靠地预测图像。

7. 发明授权

US08166423B2 Photomask design verification 失效
标题翻译：光掩模设计验证
公开(公告)号：US08166423B2
公开(公告)日：2012-04-24
申请号：US12555219
申请日：2009-09-08
申请人： Scott M. Mansfield , James A. Bruce , Gregory J. Dick , Ioana Graur
发明人： Scott M. Mansfield , James A. Bruce , Gregory J. Dick , Ioana Graur
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： Solutions for verifying photomask designs are disclosed. In one embodiment, a method of verifying a photomask design includes: simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process; simulating a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process; repeatedly simulating at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process; and generating and storing a verification result for the photomask design on a computer readable storage medium.
摘要翻译：公开了用于验证光掩模设计的解决方案。在一个实施例中，验证光掩模设计的方法包括：使用多个掩模形状和用于初始半导体制造工艺的变化模型来模拟初始半导体制造工艺，以生成用于初始半导体制造工艺的多个轮廓; 使用用于初始半导体制造工艺的轮廓和随后的半导体制造工艺的变型模型来模拟随后的半导体制造工艺，以生成用于后续半导体制造工艺的多个轮廓; 使用多个轮廓重复模拟至少一个随后的半导体制造工艺，用于随后的半导体制造工艺和用于后续半导体制造工艺的变型模型; 以及在计算机可读存储介质上生成和存储光掩模设计的验证结果。

8. 发明授权

US09087739B2 Pattern improvement in multiprocess patterning 有权
标题翻译：多进程图案化模式的改进
公开(公告)号：US09087739B2
公开(公告)日：2015-07-21
申请号：US12581422
申请日：2009-10-19
申请人： Derren N. Dunn , Ioana Graur , Scott M. Mansfield
发明人： Derren N. Dunn , Ioana Graur , Scott M. Mansfield
IPC分类号： G06F17/50 , H01L21/66 , G03F7/20 , H01L21/033 , H01L21/311 , H01L21/768
CPC分类号： H01L22/12 , G03F1/36 , G03F1/80 , G03F7/70441 , G03F7/705 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816
摘要： Improved fidelity to an integrated circuit pattern design in a semiconductor structure ultimately produced is achieved by modeling material removal and deposition processes in regard to materials, reactant, feature size, feature density, process parameters and the like as well as the effects of such parameters on etch and material deposition bias due to microloading and RIE lag (including inverse RIE lag) and using the models to work backward through the intended manufacturing method steps, including hard mask pattern decomposition, to morphologically develop feature patterns for use in most or all process steps which will result in the desired feature sizes and shapes at the completion of the overall process. Modeling of processes may be simplified through use of process assist features to locally adjust rates of material deposition and removal.
摘要翻译：通过在材料，反应物，特征尺寸，特征密度，工艺参数等方面对材料去除和沉积过程进行建模，以及这些参数对这些参数的影响，可以实现对最终生产的半导体结构中的集成电路图案设计的改进的保真度由于微加载和RIE滞后（包括反RIE滞后）导致的蚀刻和材料沉积偏差，并且使用模型通过包括硬掩模图案分解在内的预期制造方法步骤向后工作，以形态地开发用于大多数或所有工艺步骤的特征图案这将在整个过程完成时产生期望的特征尺寸和形状。可以通过使用工艺辅助特征来局部地调整材料沉积和去除速率来简化工艺的建模。

9. 发明授权

US08108804B2 Short path customized mask correction 有权
标题翻译：短路定制掩码校正
公开(公告)号：US08108804B2
公开(公告)日：2012-01-31
申请号：US12355814
申请日：2009-01-19
申请人： Ioana Graur , Scott M. Mansfield
发明人： Ioana Graur , Scott M. Mansfield
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Embodiments of the present invention provide a method of performing photo-mask correction. The method includes identifying a hot-spot in a photo-mask that violates one or more predefined rules; creating a window area in the photo-mask that surrounds the hot spot; categorizing the window area; selecting a solution, from a library of pre-computed solutions, based on a category of the window area; and applying the solution to the hot spot. A service-oriented architecture (SOA) system that synchronizes the design to the process is also provided.
摘要翻译：本发明的实施例提供一种执行光掩模校正的方法。该方法包括识别违反一个或多个预定义规则的照相掩模中的热点; 在围绕热点的照相掩模中创建一个窗口区域; 分类窗口区域; 基于窗口区域的类别从预先计算的解决方案库中选择解决方案; 并将解决方案应用于热点。还提供了将设计与流程同步的面向服务架构（SOA）系统。

10. 发明申请

US20110091815A1 Pattern Improvement in Multiprocess Patterning 有权
标题翻译：多进程模式的模式改进
公开(公告)号：US20110091815A1
公开(公告)日：2011-04-21
申请号：US12581422
申请日：2009-10-19
申请人： Derren N. Dunn , Ioana Graur , Scott M. Mansfield
发明人： Derren N. Dunn , Ioana Graur , Scott M. Mansfield
IPC分类号： G03F7/20
CPC分类号： H01L22/12 , G03F1/36 , G03F1/80 , G03F7/70441 , G03F7/705 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816
摘要： Improved fidelity to an integrated circuit pattern design in a semiconductor structure ultimately produced is achieved by modeling material removal and deposition processes in regard to materials, reactant, feature size, feature density, process parameters and the like as well as the effects of such parameters on etch and material deposition bias due to microloading and RIE lag (including inverse RIE lag) and using the models to work backward through the intended manufacturing method steps, including hard mask pattern decomposition, to morphologically develop feature patterns for use in most or all process steps which will result in the desired feature sizes and shapes at the completion of the overall process. Modeling of processes may be simplified through use of process assist features to locally adjust rates of material deposition and removal.
摘要翻译：通过在材料，反应物，特征尺寸，特征密度，工艺参数等方面对材料去除和沉积过程进行建模，以及这些参数对这些参数的影响，可以实现对最终生产的半导体结构中的集成电路图案设计的改进的保真度由于微加载和RIE滞后（包括反RIE滞后）导致的蚀刻和材料沉积偏差，并且使用模型通过包括硬掩模图案分解在内的预期制造方法步骤向后工作，以形态地开发用于大多数或所有工艺步骤的特征图案这将在整个过程完成时产生期望的特征尺寸和形状。可以通过使用工艺辅助特征来局部地调整材料沉积和去除速率来简化工艺的建模。

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