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1. 发明授权

US06355567B1 Retrograde openings in thin films 失效
标题翻译：薄膜逆行开口
公开(公告)号：US06355567B1
公开(公告)日：2002-03-12
申请号：US09345646
申请日：1999-06-30
申请人： Scott D. Halle , Paul C. Jamison , David E. Kotecki , Richard S. Wise
发明人： Scott D. Halle , Paul C. Jamison , David E. Kotecki , Richard S. Wise
IPC分类号： H01L21311
CPC分类号： H01L21/76879 , H01L21/31116 , H01L21/76804 , H01L21/7682 , H01L21/76885
摘要： Retrograde openings in thin films and the process for forming the same. The openings may include conductive materials formed within the openings to serve as a wiring pattern which includes wires having tapered cross sections. The process involves a two-step etching procedure for forming a retrograde opening within a film having a gradient of a characteristic that influences the etch rate for a chosen etchant species. An opening is first formed within the film by an anisotropic etch process. The opening is then converted to an opening including retrograde features by an isotropic etch process which is selective to the characteristic. Thereafter, the retrograde opening is filled with a conductive material, in one case, by electroplating or other deposition techniques.
摘要翻译：薄膜中的逆行开口及其形成方法。开口可以包括形成在开口内的导电材料，以用作包括具有锥形横截面的导线的布线图案。该方法涉及用于在膜内形成具有影响所选择的蚀刻剂物质的蚀刻速率的特性梯度的逆向开口的两步蚀刻方法。首先通过各向异性蚀刻工艺在膜内形成开口。然后通过对特性有选择性的各向同性蚀刻工艺将开口转换成包括逆行特征的开口。此后，逆行开口填充有导电材料，在一种情况下，通过电镀或其它沉积技术。

2. 发明授权

US06345399B1 Hard mask process to prevent surface roughness for selective dielectric etching 失效
标题翻译：硬掩模工艺，以防止表面粗糙度进行选择性电介质蚀刻
公开(公告)号：US06345399B1
公开(公告)日：2002-02-12
申请号：US09671408
申请日：2000-09-27
申请人： Paul C. Jamison , Tina Wagner , Richard S. Wise , Hongwen Yan
发明人： Paul C. Jamison , Tina Wagner , Richard S. Wise , Hongwen Yan
IPC分类号： H01L21311
CPC分类号： H01L21/0332 , H01L21/3081 , Y10S388/934
摘要： The propagation of microfissures from a photoresist to an underlying material layer during lithography and etching can be substantially prevented by placing a hard mask between the photoresist and the material layer to be etched. Specifically, the microfissure propagation is substantially prevented by (a) forming a compressive hard mask on a surface of a non-compressive material layer that is to be patterned by lithography and etching; (b) forming a patterned photoresist on said hard mask, wherein a portion of said hard mask is exposed; (c) removing said exposed portion of said hard mask so as to expose a portion of said non-compressive material layer; and (d) transferring said pattern from said patterned photoresist to said exposed portion of said material layer by etching, wherein said hard mask is selective to said etching and thus substantially prevents the propagation of photoresist microfissures to said material layer.
摘要翻译：通过在光致抗蚀剂和待蚀刻的材料层之间放置硬掩模，可以显着地防止在光刻和蚀刻期间从光致抗蚀剂到下层材料层的微结构的传播。具体地说，通过（a）在通过光刻和蚀刻被图案化的非压缩材料层的表面上形成压缩硬掩模，基本上防止了微裂纹传播; （b）在所述硬掩模上形成图案化的光致抗蚀剂，其中暴露所述硬掩模的一部分; （c）去除所述硬掩模的所述暴露部分以暴露所述非压缩材料层的一部分; 以及（d）通过蚀刻将所述图案从所述图案化的光致抗蚀剂转移到所述材料层的所述暴露部分，其中所述硬掩模对所述蚀刻具有选择性，因此基本上防止光致抗蚀剂微裂纹向所述材料层的传播。

3. 发明授权

US09006094B2 Stratified gate dielectric stack for gate dielectric leakage reduction 有权
标题翻译：用于栅介质泄漏减少的分层栅极电介质叠层
公开(公告)号：US09006094B2
公开(公告)日：2015-04-14
申请号：US13449647
申请日：2012-04-18
申请人： Hemanth Jagannathan , Paul C. Jamison
发明人： Hemanth Jagannathan , Paul C. Jamison
IPC分类号： H01L21/20 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/78 , H01L21/28
CPC分类号： H01L21/283 , H01L21/28158 , H01L21/28202 , H01L21/28211 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66795 , H01L29/7833 , H01L29/785
摘要： A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness.
摘要翻译：分层栅极电介质堆叠包括第一高介电常数（high-k）栅极电介质，其包括第一高k电介质材料，带隙破坏电介质，其包含具有与第一高k电介质不同带隙的电介质材料材料和包含第二高k电介质材料的第二高k栅极电介质。带隙破坏电介质包括介电材料的至少一个连续的原子层。因此，分层栅极电介质堆叠包括第一高k栅极电介质和带隙破坏电介质之间的第一原子界面，以及第二高k栅极电介质和带隙破坏电介质之间的第二原子界面其与带隙破坏电介质的电介质材料的至少一个连续原子层与第一原子界面间隔开。带隙干扰介质的插入导致较低的栅极泄漏，而不会导致阈值电压特性和有效氧化物厚度的任何实质性变化。

4. 发明申请

US20130280902A1 STRATIFIED GATE DIELECTRIC STACK FOR GATE DIELECTRIC LEAKAGE REDUCTION 有权
公开(公告)号：US20130280902A1
公开(公告)日：2013-10-24
申请号：US13449647
申请日：2012-04-18
申请人： Hemanth Jagannathan , Paul C. Jamison
发明人： Hemanth Jagannathan , Paul C. Jamison
IPC分类号： H01L21/28
CPC分类号： H01L21/283 , H01L21/28158 , H01L21/28202 , H01L21/28211 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66795 , H01L29/7833 , H01L29/785
摘要： A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness.

5. 发明授权

US06511876B2 High mobility FETS using A1203 as a gate oxide 有权
标题翻译：使用Al2O3作为栅极氧化物的高迁移率FET
公开(公告)号：US06511876B2
公开(公告)日：2003-01-28
申请号：US09888777
申请日：2001-06-25
申请人： Douglas A. Buchanan , Alessandro C. Callegari , Michael A. Gribelyuk , Paul C. Jamison , Deborah Ann Neumayer
发明人： Douglas A. Buchanan , Alessandro C. Callegari , Michael A. Gribelyuk , Paul C. Jamison , Deborah Ann Neumayer
IPC分类号： H01C218242
CPC分类号： H01L21/28185 , H01L21/02178 , H01L21/02271 , H01L21/02304 , H01L21/28194 , H01L21/28202 , H01L21/31616 , H01L21/3162 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of forming a high-k dielectric material which exhibits a substantially lower amount of trap charge within a gate stack region is provided. The method maintains high-temperatures (250° C. or above) such that the substrate wafer is not cooled during the various processing steps. Such a method leads to the formation of a high-k dielectric material which does not exhibit a hysteric behavior in a capacitance-voltage curve as well as an increased mobility on FETs using conventional CMOS processing.
摘要翻译：提供了一种形成在栅极堆叠区域内呈现基本较低量的陷阱电荷的高k电介质材料的方法。该方法保持高温（250℃或以上），使得在各种处理步骤期间基板晶片不被冷却。这种方法导致形成高k电介质材料，其在电容 - 电压曲线中不表现出歇斯底里行为，并且使用常规CMOS处理在FET上增加迁移率。

6. 发明授权

US09059314B2 Structure and method to obtain EOT scaled dielectric stacks 有权
标题翻译：获得EOT缩放电介质叠层的结构和方法
公开(公告)号：US09059314B2
公开(公告)日：2015-06-16
申请号：US13602118
申请日：2012-09-01
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

7. 发明授权

US08304836B2 Structure and method to obtain EOT scaled dielectric stacks 有权
标题翻译：获得EOT缩放电介质堆叠的结构和方法
公开(公告)号：US08304836B2
公开(公告)日：2012-11-06
申请号：US12620234
申请日：2009-11-17
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L21/70
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

8. 发明申请

US20110115027A1 STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS 有权
标题翻译：结构和方法来获取电子尺寸的电介质堆叠
公开(公告)号：US20110115027A1
公开(公告)日：2011-05-19
申请号：US12620234
申请日：2009-11-17
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/263
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

9. 发明授权

US07858500B2 Low threshold voltage semiconductor device with dual threshold voltage control means 有权
标题翻译：具有双阈值电压控制装置的低阈值电压半导体器件
公开(公告)号：US07858500B2
公开(公告)日：2010-12-28
申请号：US12062972
申请日：2008-04-04
申请人： Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Paul C. Jamison , Rajarao Jammy , Barry P. Linder , Vijay Narayanan
发明人： Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Paul C. Jamison , Rajarao Jammy , Barry P. Linder , Vijay Narayanan
IPC分类号： H01L21/479
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/28238 , H01L21/823807 , H01L29/105 , H01L29/1083 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.
摘要翻译：一种半导体结构，特别是pFET，其包括具有大于SiO 2的介电常数和大于50％的Ge或Si含量的介电材料和至少一种用于通过材料堆的阈值/平带电压调谐的其它装置提供工程。本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。本发明还涉及一种制造这种CMOS结构的方法。

10. 发明授权

US07169674B2 Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier 有权
标题翻译：具有高介电常数栅极电介质和集成扩散势垒的互补金属氧化物半导体（CMOS）栅极叠层
公开(公告)号：US07169674B2
公开(公告)日：2007-01-30
申请号：US11066762
申请日：2005-02-28
申请人： Nestor Alexander Bojarczuk, Jr. , Kevin Kok Chan , Christopher Peter D'Emic , Evgeni Gousev , Supratik Guha , Paul C. Jamison , Lars-Ake Ragnarsson
发明人： Nestor Alexander Bojarczuk, Jr. , Kevin Kok Chan , Christopher Peter D'Emic , Evgeni Gousev , Supratik Guha , Paul C. Jamison , Lars-Ake Ragnarsson
IPC分类号： H01L21/8236 , H01L21/8222 , H01L21/335 , H01L21/8234 , H01L21/336 , H01L21/331
CPC分类号： H01L29/513 , H01L21/28194
摘要： A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.
摘要翻译：用于具有沟道区和栅电极的场效应晶体管的扩散势垒（和形成扩散势垒的方法）包括设置在沟道区上的绝缘材料。绝缘材料包括氮（N），并且设置在栅电极下方。绝缘材料可以设置为层或分布在设置在栅电极下方的栅极电介质材料内。

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