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1. 发明授权

US5164813A New diode structure 失效
标题翻译：新二极管结构
公开(公告)号：US5164813A
公开(公告)日：1992-11-17
申请号：US700107
申请日：1991-05-08
申请人： Scott C. Blackstone , Philip L. Hower , Elizabeth M. Roughan , Christopher H. Doucette , Roy Lee , Carolyn Q. Cotnam
发明人： Scott C. Blackstone , Philip L. Hower , Elizabeth M. Roughan , Christopher H. Doucette , Roy Lee , Carolyn Q. Cotnam
IPC分类号： H01L21/18 , H01L21/329 , H01L23/051 , H01L29/861
CPC分类号： H01L29/66113 , H01L21/187 , H01L23/051 , H01L24/01 , H01L29/861 , H01L29/8613 , H01L2924/12035 , H01L2924/12036 , H01L2924/12042 , H01L2924/12043
摘要： A new diode structure is provided by bonding two semiconductor materials together having a low capacitance, a large contact area and mechanical ruggedness. The cross-sectional area of at least one of the semiconductor materials is reduced in the region of the bond resulting in a structure with either an hourglass or truncated hourglass-like cross-section. A diode PN junction is contained in the neighborhood of the area of reduced cross section. The diode so constructed provides a sufficient spacing between the unbonded semiconductor regions to reduce total packaged diode capacitance without introducing a spacer layer. The diode is processed to limit the area of the PN junction formed therein to the region of the bonding between the semiconductor materials, without limiting the metallized contact area, further controlling the diode capacitance as well as other electrical characteristics. The outer ends of the diode parallel to the bond, comprising typically P and N type semiconductor regions, are typically connected to metal leads which comprise the diode leads and the diode is packaged to form a mechanically and electrically stable low capacitance diode. This diode can be encapsulated such that no void or cavity exists within the interior of the structure without changing the diode construction process.
摘要翻译：通过将两个半导体材料结合在一起，具有低电容，大的接触面积和机械坚固性来提供新的二极管结构。至少一种半导体材料的横截面面积在结合区域中减小，从而产生具有沙漏或截短的沙漏状横截面的结构。二极管PN结包含在减小截面的区域附近。如此构造的二极管在未连接的半导体区域之间提供足够的间隔，以减少总封装的二极管电容而不引入间隔层。处理二极管以限制形成在其中的PN结的区域到半导体材料之间的接合区域，而不限制金属化接触面积，进一步控制二极管电容以及其它电特性。平行于键合的二极管的外端，通常包括P型和N型半导体区，通常连接到包括二极管引线的金属引线，并且二极管被封装以形成机械和电气稳定的低电容二极管。该二极管可以被封装成使得在结构内部不存在空隙或空腔而不改变二极管构造过程。

2. 发明申请

US20120112277A1 INTEGRATED LATERAL HIGH VOLTAGE MOSFET 有权
标题翻译：集成式横向高压MOSFET
公开(公告)号：US20120112277A1
公开(公告)日：2012-05-10
申请号：US13284011
申请日：2011-10-28
申请人： Marie Denison , Sameer Pendharkar , Philip L. Hower
发明人： Marie Denison , Sameer Pendharkar , Philip L. Hower
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L21/265 , H01L21/823814 , H01L27/0922 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.
摘要翻译：一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。

3. 发明申请

US20110073955A1 ISOLATION TRENCH WITH ROUNDED CORNERS FOR BiCMOS PROCESS 有权
标题翻译：用于BiCMOS工艺的带圆角的隔离开关
公开(公告)号：US20110073955A1
公开(公告)日：2011-03-31
申请号：US12962159
申请日：2010-12-07
申请人： Sameer P. Pendharkar , John Lin , Philip L. Hower , Steven L. Merchant
发明人： Sameer P. Pendharkar , John Lin , Philip L. Hower , Steven L. Merchant
IPC分类号： H01L27/06
CPC分类号： H01L21/8249 , H01L21/76232 , H01L27/0623
摘要： A semiconductor device comprising a first transistor device (130) on or in a semiconductor substrate (115) and a second transistor device (132) on or in the substrate. The device further comprises an insulating trench (200) located between the first transistor device and the second transistor device. At least one upper corner (610) of the insulating trench is a rounded corner in a lateral plane (620) of the substrate.
摘要翻译：一种半导体器件，包括在半导体衬底（115）上或半导体衬底（115）中的第一晶体管器件（130）和衬底上或衬底中的第二晶体管器件（132）。该器件还包括位于第一晶体管器件和第二晶体管器件之间的绝缘沟槽（200）。绝缘沟槽的至少一个上角（610）是衬底的横向平面（620）中的圆角。

4. 发明授权

US4042947A High voltage transistor with high gain 失效
标题翻译：具有高增益的高压晶体管
公开(公告)号：US4042947A
公开(公告)日：1977-08-16
申请号：US646794
申请日：1976-01-06
申请人： Chang K. Chu , Philip L. Hower , George W. Vomish
发明人： Chang K. Chu , Philip L. Hower , George W. Vomish
IPC分类号： H01L21/331 , H01L29/08 , H01L29/417 , H01L29/73 , H01L29/732 , H01L29/72
CPC分类号： H01L29/41708 , H01L29/0804 , H01L29/732
摘要： A transistor device is described in which an NPN semiconductor structure has a specially adapted N-type emitter zone and associated electrode. The emitter zone is produced by etching a cavity in one major surface of the semiconductor body followed by diffusion of N-type dopant material. Emitter, base and collector electrodes are then affixed to the appropriate surfaces of the body to provide electrical and thermal contact thereto.
摘要翻译：描述了一种晶体管器件，其中NPN半导体结构具有特别适合的N型发射极区和相关电极。通过蚀刻半导体主体的一个主表面中的空腔，然后N型掺杂剂材料的扩散来产生发射极区。然后将发射极，基极和集电极固定到主体的适当表面以提供与其的电接触和热接触。

5. 发明授权

US09806190B2 High voltage drain extension on thin buried oxide SOI 有权
公开(公告)号：US09806190B2
公开(公告)日：2017-10-31
申请号：US13282305
申请日：2011-10-26
申请人： Marie Denison , Philip L. Hower , Sameer Pendharkar
发明人： Marie Denison , Philip L. Hower , Sameer Pendharkar
IPC分类号： H01L29/78 , H01L21/336 , H01L27/12 , H01L29/10 , H01L29/861 , H01L27/06
CPC分类号： H01L29/7824 , H01L27/0629 , H01L27/1203 , H01L29/1087 , H01L29/7818 , H01L29/7835 , H01L29/861
摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

6. 发明授权

US08853029B2 Method of making vertical transistor with graded field plate dielectric 有权
标题翻译：制造具有梯度场板电介质的垂直晶体管的方法
公开(公告)号：US08853029B2
公开(公告)日：2014-10-07
申请号：US13188162
申请日：2011-07-21
申请人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
发明人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/423
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66719 , H01L29/66734
摘要： An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.
摘要翻译：电子器件具有形成在半导体层中的多个沟槽。垂直漂移区域位于沟槽之间和相邻的沟槽之间。电极位于每个沟槽内，电极具有栅电极部分和场板部分。在场板部分和垂直漂移区域之间设置具有较大深度的厚度增加的分级场板电介质。

7. 发明授权

US08728846B2 Vertical thermoelectric structures 有权
标题翻译：垂直热电结构
公开(公告)号：US08728846B2
公开(公告)日：2014-05-20
申请号：US12544548
申请日：2009-08-20
申请人： Barry Jon Male , Philip L. Hower
发明人： Barry Jon Male , Philip L. Hower
IPC分类号： H01L29/66
CPC分类号： H01L35/30 , H01L23/38 , H01L27/16 , H01L35/22 , H01L35/32 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.
摘要翻译：公开了一种热电装置，其包括从IC的顶表面突出的金属热端子，其连接到由IC的互连元件制成的垂直导热导管。侧向热电元件在一端连接到垂直导管，并在另一端与IC基板相互散热。侧向热电元件通过顶侧的互连电介质材料和底侧的场氧化物热隔离。当在发电机模式下工作时，金属热端子连接到热源，并且IC基板连接到散热器。热功率流过垂直管道到横向热电元件，产生电位。电位可以施加到IC中的元件或电路。热电装置可以集成到IC中而不增加制造成本或复杂性。

8. 发明申请

US20120104497A1 HIGH VOLTAGE DRAIN EXTENSION ON THIN BURIED OXIDE SOI 有权
标题翻译：稀土氧化物SOI上的高压漏电延伸
公开(公告)号：US20120104497A1
公开(公告)日：2012-05-03
申请号：US13282305
申请日：2011-10-26
申请人： Marie Denison , Philip L. Hower , Sameer Pendharkar
发明人： Marie Denison , Philip L. Hower , Sameer Pendharkar
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7824 , H01L27/0629 , H01L27/1203 , H01L29/1087 , H01L29/7818 , H01L29/7835 , H01L29/861
摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).
摘要翻译： SOI衬底上的集成电路，其包含在漏极（n沟道）或体区（p沟道）中具有穿通衬底二极管的扩展漏极MOS晶体管，使得漏极或体区域通过pn耦合到处理晶片交界处在SOI衬底上的集成电路，其包含通过pn结耦合到处理晶片的漏极（n沟道）或体区（p沟道）中的贯穿衬底二极管的延伸漏极MOS晶体管，其与排水或身体区域。在包含漏极（n沟道）或体区（p沟道）中的贯通衬底二极管的延伸漏极MOS晶体管的SOI衬底上形成集成电路的工艺。

9. 发明授权

US07910417B2 Distributed high voltage JFET 有权
标题翻译：分布式高电压JFET
公开(公告)号：US07910417B2
公开(公告)日：2011-03-22
申请号：US12176488
申请日：2008-07-21
申请人： Philip L. Hower , David A. Walch , John Lin , Steven L. Merchant
发明人： Philip L. Hower , David A. Walch , John Lin , Steven L. Merchant
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L29/1066
摘要： A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.
摘要翻译：结型场效应晶体管（JFET）可以制造具有阱区，阱区包括平均掺杂剂浓度基本上小于阱区的剩余部分的平均掺杂浓度的沟道区。与阱区域的其余部分相比，沟道区域的较低平均掺杂浓度降低了JFET的夹断电压。

10. 发明授权

US06624481B1 ESD robust bipolar transistor with high variable trigger and sustaining voltages 有权
标题翻译：具有高可变触发和维持电压的ESD稳健双极晶体管
公开(公告)号：US06624481B1
公开(公告)日：2003-09-23
申请号：US10407037
申请日：2003-04-04
申请人： Sameer P. Pendharkar , Philip L. Hower , Robert Steinhoff
发明人： Sameer P. Pendharkar , Philip L. Hower , Robert Steinhoff
IPC分类号： H01L2362
CPC分类号： H01L27/0259 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： An ESD robust bipolar transistor (200) that includes first and second bipolar elements (210, 220), wherein a first trigger voltage of the first bipolar element (210) is proximate a second sustaining voltage of the second bipolar element (220). The first and second bipolar elements (210, 220) include first and second bases (214, 224), emitters (216, 226) and collectors (212, 222), respectively. The first and second bases (214, 224) are coupled and the first and second collectors (212, 222) are coupled. The ESD robust bipolar transistor (200) also includes an emitter resistor (250) and a base resistor (260), wherein the emitter resistor (250) couples the first and second emitters (216, 226) and the base resistor (260) couples the second emitter (226) and the first and second bases (214, 224).
摘要翻译：包括第一和第二双极元件（210,220）的ESD坚固的双极晶体管（200），其中第一双极元件（210）的第一触发电压接近第二双极元件（220）的第二维持电压。第一和第二双极元件（210,220）分别包括第一和第二基极（214,224），发射极（216,226）和集电极（212,222）。耦合第一和第二基极（214,224），并且耦合第一和第二集电极（212,222）。 ESD稳健双极晶体管（200）还包括发射极电阻（250）和基极电阻（260），其中发射极电阻（250）将第一和第二发射极（216,226）和基极电阻（260）耦合第二发射器（226）和第一和第二基极（214,224）。

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