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1. 发明授权

US07269706B2 Adaptive incremental checkpointing 失效
标题翻译：自适应增量检查点
公开(公告)号：US07269706B2
公开(公告)日：2007-09-11
申请号：US11008525
申请日：2004-12-09
申请人： Saurabh Agarwal , Rahul Garg , Meeta S Gupta
发明人： Saurabh Agarwal , Rahul Garg , Meeta S Gupta
IPC分类号： G06F12/00
CPC分类号： G06F11/1451
摘要： A method, apparatus and computer program product are disclosed for incrementally checkpointing the state of a computer memory in the presence of at least one executing software application at periodic instants. A secure hash function is periodically applied to each partitioned contiguous block of memory to give a periodic block hash value. At each periodic instant, a block hash value for each block is compared with a respective preceding block hash value to determine if said memory block has changed according to whether said block hash values are different. Only changed memory blocks are stored in a checkpoint record. The memory block sizes are adapted at each periodic instant to split changed blocks into at least two parts and to merge only two non-changed contiguous blocks at a time.
摘要翻译：公开了一种方法，装置和计算机程序产品，用于在周期性时刻在存在至少一个执行软件应用的情况下递增地检查计算机存储器的状态。周期性地对每个分区的连续的存储器块应用安全的散列函数以给出周期性的块哈希值。在每个周期性时刻，将每个块的块哈希值与相应的先前块散列值进行比较，以根据所述块哈希值是否不同来确定所述存储块是否已经改变。只有更改的内存块才被存储在检查点记录中。存储器块大小在每个周期性时刻被适配，以将改变的块分成至少两个部分，并且一次仅合并两个未改变的连续块。

2. 发明申请

US20060129610A1 Adaptive incremental checkpointing 失效
标题翻译：自适应增量检查点
公开(公告)号：US20060129610A1
公开(公告)日：2006-06-15
申请号：US11008525
申请日：2004-12-09
申请人： Saurabh Agarwal , Rahul Garg , Meeta Gupta
发明人： Saurabh Agarwal , Rahul Garg , Meeta Gupta
IPC分类号： G06F17/30
CPC分类号： G06F11/1451
摘要： A method, apparatus and computer program product are disclosed for incrementally checkpointing the state of a computer memory in the presence of at least one executing software application at periodic instants. A secure hash function is periodically applied to each partitioned contiguous block of memory to give a periodic block hash value. At each periodic instant, a block hash value for each block is compared with a respective preceding block hash value to determine if said memory block has changed according to whether said block hash values are different. Only changed memory blocks are stored in a checkpoint record. The memory block sizes are adapted at each periodic instant to split changed blocks into at least two parts and to merge only two non-changed contiguous blocks at a time.
摘要翻译：公开了一种方法，装置和计算机程序产品，用于在周期性时刻在存在至少一个执行软件应用的情况下递增地检查计算机存储器的状态。周期性地对每个分区的连续的存储器块应用安全的散列函数以给出周期性的块哈希值。在每个周期性时刻，将每个块的块哈希值与相应的先前块散列值进行比较，以根据所述块哈希值是否不同来确定所述存储块是否已经改变。只有更改的内存块才被存储在检查点记录中。存储器块大小在每个周期性时刻被适配，以将改变的块分成至少两个部分，并且一次仅合并两个未改变的连续块。

3. 发明授权

US07974181B2 Systems and methods for transmit-only peak-to-average ratio reduction in the oversampled regime using reserved tones 有权
标题翻译：使用保留色调的过采样方案中仅发送峰到峰比降低的系统和方法
公开(公告)号：US07974181B2
公开(公告)日：2011-07-05
申请号：US12138731
申请日：2008-06-13
申请人： Amitkumar Mahadevan , Patrick Duvaut , Harish Jethanandani , Rahul Garg
发明人： Amitkumar Mahadevan , Patrick Duvaut , Harish Jethanandani , Rahul Garg
IPC分类号： H04J11/00
CPC分类号： H04L27/2618
摘要： Systems and methods for reducing the peak-to-average power ratio (PAR) at the transmitter can reduce the dynamic range required in various analog components. PAR can be reduced by applying a time-domain compensation signal in the oversampled regime, using tones reserved for PAR reduction. A set of vectors corresponding to PAR tones is generated by processing out-of-phase symbols for each PAR tone to form a span matrix. The span matrix is used to find a best fit of a desired target signal to a time-domain compensation signal comprising only PAR tones.
摘要翻译：用于降低发射机的峰均功率比（PAR）的系统和方法可以减少各种模拟组件所需的动态范围。可以通过在过采样方案中应用时域补偿信号，使用保留给PAR减少的音调来减少PAR。通过处理每个PAR色调的异相符号来生成对应于PAR色调的一组矢量以形成跨度矩阵。跨度矩阵用于找到期望目标信号对仅包括PAR色调的时域补偿信号的最佳拟合。

4. 发明申请

US20100061437A1 Systems and Methods for Impulse Noise Characterization 有权
标题翻译：脉冲噪声表征系统与方法
公开(公告)号：US20100061437A1
公开(公告)日：2010-03-11
申请号：US12348565
申请日：2009-01-05
申请人： Hemant Samdani , Kunal Raheja , Rahul Garg , Amitkumar Mahadevan , Patrick Duvaut
发明人： Hemant Samdani , Kunal Raheja , Rahul Garg , Amitkumar Mahadevan , Patrick Duvaut
IPC分类号： H04B17/00
CPC分类号： H04B3/46
摘要： Impulse noise from nearby or intense electrical sources can disrupt communications over digital subscriber lines (DSL). The characterization of the nature, timing and length of impulse noise sources present on a DSL loop is a critical first step in mitigating the effect of impulse noise on DSL communications. DSL standards provide histograms for impulse length and inter-arrival time of impulses. These histograms can be used to derive the nature, maximum frequency and other statistics related to impulse noise on a DSL line.
摘要翻译：来自附近或强电场的脉冲噪声可能会扰乱通过数字用户线路（DSL）的通信。存在于DSL环路上的脉冲噪声源的性质，时间和长度的表征是减轻脉冲噪声对DSL通信的影响的关键的第一步。 DSL标准提供脉冲长度和脉冲到达间隔时间的直方图。这些直方图可用于导出与DSL线路上的脉冲噪声有关的性质，最大频率和其他统计。

5. 发明授权

US07613981B2 System and method for reducing power consumption in a low-density parity-check (LDPC) decoder 有权
标题翻译：一种降低低密度奇偶校验（LDPC）解码器功耗的系统和方法
公开(公告)号：US07613981B2
公开(公告)日：2009-11-03
申请号：US11851383
申请日：2007-09-06
申请人： Rahul Garg , Amrit Singh
发明人： Rahul Garg , Amrit Singh
IPC分类号： H03M13/00
CPC分类号： H03M13/114 , H03M13/1111 , H03M13/1117 , H03M13/3738 , H03M13/3753 , H03M13/6502 , H03M13/6527 , H03M13/6544
摘要： A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module checks whether a check node is in sleep mode. The check node is considered to be in sleep mode when the absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value. The gating circuit turns OFF a Check Node and Bit Node Update Unit (CNBNU) associated with the check node when the check node is in the sleep mode. Turning OFF a CNBNU stops the exchange of messages between the check node and its corresponding one or more bit nodes.
摘要翻译：用于降低低密度奇偶校验码（LDPC）解码器中的功耗的系统和方法包括睡眠模式检查模块和门控电路。睡眠模式检查模块检查校验节点是否处于睡眠模式。当到达对应于校验节点的一个或多个比特节点中的每一个的消息的绝对值大于阈值时，该校验节点被认为处于睡眠模式。当校验节点处于睡眠模式时，门控电路关闭与校验节点相关联的校验节点和位节点更新单元（CNBNU）。关闭CNBNU会停止校验节点与其相应的一个或多个位节点之间的消息交换。

6. 发明授权

US07463681B2 Architecture for feedback loops in decision feedback equalizers 有权
标题翻译：决策反馈均衡器中反馈回路的架构
公开(公告)号：US07463681B2
公开(公告)日：2008-12-09
申请号：US11121475
申请日：2005-05-04
申请人： Rahul Garg , Kiran Devanahalli , Aparna Chakrakodi Krishnashastry
发明人： Rahul Garg , Kiran Devanahalli , Aparna Chakrakodi Krishnashastry
IPC分类号： H03H7/30 , H03H7/40
CPC分类号： H04L23/02 , H04L25/03057 , H04L2025/03566
摘要： A decision feedback equalizer (DFE) has an inter symbol interference (ISI) loop and inter chip interference (ICI) loop. A buffer at the input of the DFE loop receives a (CCK based data rate) signal coming into the DFE, retains a predetermined number of chips from each incoming symbol and assists to meet timing requirements by chip management. An outgoing rate for the chips from the buffer may depend on the incoming rate and may be higher than the incoming rate by a known factor. A method of designing a configuration for the DFE takes into consideration the timing delay in the loops. The operation within the DFE loop is pipelined, and any latency due to the pipelining is handled at a CCK demodulator. A method for designing the DFE architecture and an article comprising a storage medium with instructions thereon for executing the method, are also disclosed.
摘要翻译：判决反馈均衡器（DFE）具有符号间干扰（ISI）环路和芯片间干扰（ICI）环路。 DFE循环输入端的一个缓冲器接收到进入DFE的基于（基于CCK的数据速率）信号，从每个输入符号保留预定数量的芯片，并通过芯片管理帮助满足定时要求。来自缓冲器的芯片的输出速率可以取决于输入速率，并且可以通过已知因素高于输入速率。设计DFE的配置的方法考虑了循环中的定时延迟。 DFE循环中的操作是流水线的，并且由于流水线的任何延迟在CCK解调器处理。还公开了一种用于设计DFE架构的方法和包括其上具有用于执行该方法的指令的存储介质的物品。

7. 发明授权

US06976005B1 Methods, systems, and computer program products for dynamically bidding in and conducting multiple simultaneous online auctions located across multiple online auction sites 失效
标题翻译：方法，系统和计算机程序产品，用于在多个在线拍卖站点上动态投标并进行多个同时在线拍卖
公开(公告)号：US06976005B1
公开(公告)日：2005-12-13
申请号：US09667169
申请日：2000-09-21
申请人： Vipul Bansal , Rahul Garg
发明人： Vipul Bansal , Rahul Garg
IPC分类号： G06Q30/06 , G06Q30/08 , G06F17/60
CPC分类号： G06Q40/04 , G06Q30/0617 , G06Q30/08
摘要： The use of software-based agents to act on behalf of human bidders for dynamic participation in multiple simultaneous online auctions is disclosed. The software-based agents may reside on computer systems or on any type of stationary or mobile terminal. On the basis of bidding-related information from a bidder, a software agent selects a plurality of auctions to place bids in. Upon being outbid, the agent determines whether to place an additional bid in a further auction. The agent can make such a determination on the basis of maximising profitability or surplus.
摘要翻译：公开了使用基于软件的代理人代表人类投标人动态参与多个同时在线拍卖。基于软件的代理可以驻留在计算机系统或任何类型的固定或移动终端上。根据投标人的投标相关信息，软件代理人选择多个拍卖进行投标。经过一段时间后，代理商确定是否在进一步的拍卖中再次出价。代理人可以在最大化盈利能力或盈余的基础上做出这样的决定。

8. 发明授权

US08379947B2 Spatio-temporal image reconstruction using sparse regression and secondary information 有权
标题翻译：使用稀疏回归和二次信息的时空图像重建
公开(公告)号：US08379947B2
公开(公告)日：2013-02-19
申请号：US12790199
申请日：2010-05-28
申请人： Rahul Garg , Monu Kedia , Yogish Sabharwal
发明人： Rahul Garg , Monu Kedia , Yogish Sabharwal
IPC分类号： G06K9/00
CPC分类号： G06T11/006 , G06T2211/412 , G06T2211/424
摘要： A spatio-temporal image of an object is reconstructed based on captured data characterizing the object. The spatio-temporal image comprises a plurality of spatial images in respective time intervals, and at least a given one of the spatial images in one of the time intervals is reconstructed using not only captured data from a frame associated with that time interval but also captured data associated with one or more additional frames associated with other time intervals. The spatio-temporal image may be reconstructed by iteratively obtaining a solution to a minimization or maximization problem in a sparse domain and transforming the solution to an image domain. The transformation between the sparse domain and the image domain may utilize a spatio-temporal transformation implemented using a plurality of basis functions, one or more of which may be determined at least in part based on secondary information associated with the imaged object.
摘要翻译：基于表征对象的捕获数据来重构对象的时空图像。空间 - 时间图像包括各个时间间隔中的多个空间图像，并且使用不仅来自与该时间间隔相关联的帧的捕获数据来重构时间间隔之一中的至少一个空间图像中的给定的一个，而且还捕获与与其他时间间隔相关联的一个或多个附加帧相关联的数据。可以通过迭代地获得稀疏域中的最小化或最大化问题的解决方案并将解决方案转换为图像域来重构时空图像。稀疏域和图像域之间的变换可以利用使用多个基本函数实现的时空变换，其中的一个或多个可以至少部分地基于与成像对象相关联的次要信息来确定。

9. 发明申请

US20130034277A1 SYSTEMS AND METHODS FOR MODELING AND PROCESSING FUNCTIONAL MAGNETIC RESONANCE IMAGE DATA USING FULL-BRAIN VECTOR AUTO-REGRESSIVE MODEL 有权
标题翻译：使用全脑向量自动调节模型建模和处理功能磁共振图像数据的系统和方法
公开(公告)号：US20130034277A1
公开(公告)日：2013-02-07
申请号：US13197011
申请日：2011-08-03
申请人： Guillermo A. Cecchi , Rahul Garg , Ravishankar Rao
发明人： Guillermo A. Cecchi , Rahul Garg , Ravishankar Rao
IPC分类号： G06K9/00 , G06G7/60
CPC分类号： G06F19/3443 , G01R33/4806 , G06F19/00 , G06F19/321 , G06T7/0012 , G06T11/003 , G06T2207/10016 , G06T2207/10076 , G06T2207/10088 , G06T2207/30016 , G16H50/20 , G16H50/70
摘要： Systems and methods for modeling functional magnetic resonance image datasets using a multivariate auto-regressive model which captures temporal dynamics in the data, and creates a reduced representation of the dataset representative of functional connectivity of voxels with respect to brain activity. Raw spatio-temporal data is processed using a multivariate auto-regressive model, wherein coefficients in the model with high weights are retained as indices that best describe the full spatio-temporal data. When there are a relatively small number of temporal samples of the data, sparse regression techniques are used to build the model. The model coefficients are used to perform data processing functions such as indexing, prediction, and classification.
摘要翻译：使用多变量自回归模型来建模功能性磁共振图像数据集的系统和方法，其捕获数据中的时间动力学，并且创建代表体素相对于大脑活动的功能连通性的数据集的减少的表示。使用多变量自回归模型处理原始时空数据，其中具有高权重的模型中的系数被保留为最好地描述全部时空数据的指标。当数据的时间样本数量相对较少时，使用稀疏回归技术构建模型。模型系数用于执行索引，预测和分类等数据处理功能。

10. 发明授权

US08290033B2 Systems and methods for performing combined equalization in communication systems 有权
标题翻译：用于在通信系统中执行组合均衡的系统和方法
公开(公告)号：US08290033B2
公开(公告)日：2012-10-16
申请号：US12351071
申请日：2009-01-09
申请人： Rahul Garg , Kunal Lal , Devesh Chauhan , Patrick Duvaut
发明人： Rahul Garg , Kunal Lal , Devesh Chauhan , Patrick Duvaut
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L25/03159 , H04L2025/03414 , H04L2025/03605 , H04L2025/03617
摘要： A system is described for performing combined equalization. The system comprises a time domain equalizer (TEQ) configured to receive a signal and shorten a CIR (channel impulse response) of the received signal, a Fast Fourier Transform (FFT) module for demodulating the received signal, and an equalization block for reducing inter-carrier interference (ICI) and inter-symbol interference (ISI). The equalization block comprises at least one of: a feed forward equalizer and a feed back equalizer. The system further comprises a slicer circuit configured to generate a hard-limited decision for a symbol corresponding to the received signal.
摘要翻译：描述了用于执行组合均衡的系统。该系统包括被配置为接收信号并缩短接收信号的CIR（信道脉冲响应）的时域均衡器（TEQ），用于解调接收信号的快速傅里叶变换（FFT）模块，以及用于减少接收信号的均衡块载波干扰（ICI）和符号间干扰（ISI）。均衡块包括以下中的至少一个：前馈均衡器和反馈均衡器。该系统还包括限幅器电路，被配置为产生对应于接收信号的符号的硬限制判定。

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