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1. 发明授权

US07463681B2 Architecture for feedback loops in decision feedback equalizers 有权
标题翻译：决策反馈均衡器中反馈回路的架构
公开(公告)号：US07463681B2
公开(公告)日：2008-12-09
申请号：US11121475
申请日：2005-05-04
申请人： Rahul Garg , Kiran Devanahalli , Aparna Chakrakodi Krishnashastry
发明人： Rahul Garg , Kiran Devanahalli , Aparna Chakrakodi Krishnashastry
IPC分类号： H03H7/30 , H03H7/40
CPC分类号： H04L23/02 , H04L25/03057 , H04L2025/03566
摘要： A decision feedback equalizer (DFE) has an inter symbol interference (ISI) loop and inter chip interference (ICI) loop. A buffer at the input of the DFE loop receives a (CCK based data rate) signal coming into the DFE, retains a predetermined number of chips from each incoming symbol and assists to meet timing requirements by chip management. An outgoing rate for the chips from the buffer may depend on the incoming rate and may be higher than the incoming rate by a known factor. A method of designing a configuration for the DFE takes into consideration the timing delay in the loops. The operation within the DFE loop is pipelined, and any latency due to the pipelining is handled at a CCK demodulator. A method for designing the DFE architecture and an article comprising a storage medium with instructions thereon for executing the method, are also disclosed.
摘要翻译：判决反馈均衡器（DFE）具有符号间干扰（ISI）环路和芯片间干扰（ICI）环路。 DFE循环输入端的一个缓冲器接收到进入DFE的基于（基于CCK的数据速率）信号，从每个输入符号保留预定数量的芯片，并通过芯片管理帮助满足定时要求。来自缓冲器的芯片的输出速率可以取决于输入速率，并且可以通过已知因素高于输入速率。设计DFE的配置的方法考虑了循环中的定时延迟。 DFE循环中的操作是流水线的，并且由于流水线的任何延迟在CCK解调器处理。还公开了一种用于设计DFE架构的方法和包括其上具有用于执行该方法的指令的存储介质的物品。

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