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1. 发明申请

US20070045425A1 Memory card 有权
标题翻译：存储卡
公开(公告)号：US20070045425A1
公开(公告)日：2007-03-01
申请号：US11508243
申请日：2006-08-23
申请人： Satoshi Yoshida , Nagamasa Mizushima , Shinsuke Asari , Shigeo Kurakata , Makoto Obata
发明人： Satoshi Yoshida , Nagamasa Mizushima , Shinsuke Asari , Shigeo Kurakata , Makoto Obata
IPC分类号： G06K19/06
CPC分类号： G06K19/077 , G06F13/4239 , G11C7/20
摘要： A memory card has external interface terminals, an interface controller connected to each of the terminals, a rewritable nonvolatile memory connected to the interface controller, and a data processor connected to the interface controller. The interface controller can perform an operation based on another command supplied from the outside in parallel with the operations of transferring a command for a data process supplied from the outside to the data processor and operating it. The interface controller has plural buffers and, after completely inputting the command for a data process from an outside to a first buffer of the plural buffers, allows data related to the other command supplied from the outside to be inputted to a second buffer of the plural buffers. The memory card can receive a command data and data to be processed subsequently from the outside without the need of waiting for the completion of the communication process between the data processor and the interface controller.
摘要翻译：存储卡具有外部接口端子，连接到每个端子的接口控制器，连接到接口控制器的可重写非易失性存储器和连接到接口控制器的数据处理器。接口控制器可以基于从外部向数据处理器提供的数据处理的命令的传送与数据处理器的操作并行地执行基于从外部提供的另一命令的操作并进行操作。接口控制器具有多个缓冲器，并且在从外部向多个缓冲器的第一缓冲器完全输入数据处理命令之后，允许与从外部提供的其他命令相关的数据被输入到多个缓冲器的第二缓冲器缓冲区存储卡可以从外部接收要处理的命令数据和数据，而不需要等待数据处理器和接口控制器之间的通信处理的完成。

2. 发明授权

US07708195B2 Memory card 有权
标题翻译：存储卡
公开(公告)号：US07708195B2
公开(公告)日：2010-05-04
申请号：US11508243
申请日：2006-08-23
申请人： Satoshi Yoshida , Nagamasa Mizushima , Shinsuke Asari , Shigeo Kurakata , Makoto Obata
发明人： Satoshi Yoshida , Nagamasa Mizushima , Shinsuke Asari , Shigeo Kurakata , Makoto Obata
IPC分类号： G06K5/00 , G06K19/06 , G06K7/06
CPC分类号： G06K19/077 , G06F13/4239 , G11C7/20
摘要： A memory card has external interface terminals, an interface controller connected to each of the terminals, a rewritable nonvolatile memory connected to the interface controller, and a data processor connected to the interface controller. The interface controller can perform an operation based on another command supplied from the outside in parallel with the operations of transferring a command for a data process supplied from the outside to the data processor and operating it. The interface controller has plural buffers and, after completely inputting the command for a data process from an outside to a first buffer of the plural buffers, allows data related to the other command supplied from the outside to be inputted to a second buffer of the plural buffers. The memory card can receive a command data and data to be processed subsequently from the outside without the need of waiting for the completion of the communication process between the data processor and the interface controller.
摘要翻译：存储卡具有外部接口端子，连接到每个端子的接口控制器，连接到接口控制器的可重写非易失性存储器和连接到接口控制器的数据处理器。接口控制器可以基于从外部向数据处理器提供的数据处理的命令的传送与数据处理器的操作并行地执行基于从外部提供的另一命令的操作并进行操作。接口控制器具有多个缓冲器，并且在从外部向多个缓冲器的第一缓冲器完全输入数据处理命令之后，允许与从外部提供的其他命令相关的数据被输入到多个缓冲器的第二缓冲器缓冲区存储卡可以从外部接收要处理的命令数据和数据，而不需要等待数据处理器和接口控制器之间的通信处理的完成。

3. 发明授权

US08612830B2 Method of correcting error of flash memory device, and, flash memory device and storage system using the same 有权
标题翻译：闪存装置的误差校正方法以及使用其的闪存装置及存储系统
公开(公告)号：US08612830B2
公开(公告)日：2013-12-17
申请号：US12026738
申请日：2008-02-06
申请人： Jun Kitahara , Nagamasa Mizushima
发明人： Jun Kitahara , Nagamasa Mizushima
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C16/3418
摘要： According to this invention, a highly reliable memory device that uses up a life of a flash memory can be provided. The memory device is a nonvolatile memory device including a plurality of memory cells, in which: each of the plurality of memory cells is an FET which includes a floating gate; the plurality of memory cells are divided into a plurality of deletion blocks; and the nonvolatile memory device reads data stored in a first deletion block, detects and corrects an error contained in the read data, stores, when the number of bits of the detected error exceeds a threshold, the corrected data in a second deletion block, sets a smaller value as the threshold as an error frequency detected in the first deletion block is higher, and sets a smaller value as the threshold as the number of deletion times executed in the first deletion block is larger.
摘要翻译：根据本发明，可以提供使用快闪存储器寿命的高度可靠的存储器件。存储器件是包括多个存储单元的非易失性存储器件，其中：多个存储器单元中的每一个都是包括浮置栅极的FET; 多个存储单元被分成多个删除块; 并且非易失性存储器件读取存储在第一删除块中的数据，检测并校正读取数据中包含的错误，当检测到的错误的位数超过阈值时，存储第二删除块中的校正数据作为在第一删除块中检测到的错误频率的阈值的较小值较高，并且随着在第一删除块中执行的删除次数的数量较大，将较小的值设置为阈值。

4. 发明申请

US20080126678A1 SEMICONDUCTOR MEMORY SYSTEM FOR FLASH MEMORY 失效
标题翻译：闪存存储器半导体存储器系统
公开(公告)号：US20080126678A1
公开(公告)日：2008-05-29
申请号：US11616932
申请日：2006-12-28
申请人： Nagamasa Mizushima
发明人： Nagamasa Mizushima
IPC分类号： G06F12/02
CPC分类号： G11C16/349 , G06F11/1068 , G11C5/04 , G11C16/04 , G11C16/3495 , G11C29/4401 , G11C29/46 , G11C29/76 , G11C2029/0409 , G11C2029/0411
摘要： Provided is a semiconductor memory system including a plurality of main memory chips and sub-memory chips as alternatives, in which each main memory chip includes a plurality of reserved memory blocks in the same chip as alternatives to an abnormal memory block. When it is detected that the number of the remaining reserved memory blocks unused as blocks to be reassigned has reached a first predetermined value in the main memory chip, the memory blocks in the sub-memory chip starts to be formatted. When the number of the remaining reserved memory blocks unused in the main memory chip reaches a second predetermined value, read/write with respect to the main memory chip is switched to the sub-memory chip, while bypassing the format process for the memory block in the sub-memory chip. Thus, in the semiconductor memory system including a main flash memory, an alternative flash memory, and a write cache memory, the capacity of a RAM for the write cache memory can be reduced.
摘要翻译：提供了一种半导体存储器系统，其包括作为替代的多个主存储器芯片和子存储器芯片，其中每个主存储器芯片包括与替代异常存储器块相同的芯片中的多个保留存储器块。当检测到未被使用的剩余保留存储器块的数量将被重新分配的块已经达到主存储器芯片中的第一预定值时，子存储器芯片中的存储块开始被格式化。当在主存储器芯片中未使用的剩余保留存储器块的数量达到第二预定值时，相对于主存储器芯片的读/写切换到子存储器芯片，同时绕过存储块的格式化处理子存储芯片。因此，在包括主闪速存储器，备用闪存和写入高速缓冲存储器的半导体存储器系统中，可以减少写入高速缓冲存储器的RAM的容量。

5. 发明授权

US08823817B2 Camera management device and network camera system 有权
标题翻译：相机管理设备和网络摄像机系统
公开(公告)号：US08823817B2
公开(公告)日：2014-09-02
申请号：US13204019
申请日：2011-08-05
申请人： Takeshi Asahi , Masuo Oku , Nagamasa Mizushima , Nobuhiro Yokoi
发明人： Takeshi Asahi , Masuo Oku , Nagamasa Mizushima , Nobuhiro Yokoi
IPC分类号： H04N5/232
CPC分类号： H04N5/23206
摘要： The present invention is based upon a camera management device coupled to a network camera via a network and the camera management device is provided with an image receiving unit that receives image data projected by the network camera and including control information for controlling the network camera from the network camera, a control information extracting unit that extracts the control information from the image data received by the image receiving unit and a control transmitting unit that transmits a control command according to the control information to the network camera via the network.
摘要翻译：本发明基于经由网络耦合到网络摄像机的相机管理装置，并且相机管理装置设置有图像接收单元，其接收由网络摄像机投影的图像数据，并且包括用于从网络摄像机控制的控制信息网络摄像机，控制信息提取单元，其从由图像接收单元接收的图像数据中提取控制信息;以及控制发送单元，其通过网络向网络摄像机发送根据控制信息的控制命令。

6. 发明授权

US08417896B2 Semiconductor memory system having a snapshot function 有权
标题翻译：具有快照功能的半导体存储器系统
公开(公告)号：US08417896B2
公开(公告)日：2013-04-09
申请号：US13422644
申请日：2012-03-16
申请人： Nagamasa Mizushima
发明人： Nagamasa Mizushima
IPC分类号： G06F11/00 , G06F12/00 , G11C16/02
CPC分类号： G06F12/0246 , G06F11/1415 , G06F11/1471 , G06F12/1009 , G06F2201/84
摘要： In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request. The semiconductor memory computer includes a page status register for detecting one page status allocated to each page, and page statuses to be detected include the at least following four statuses: (1) a latest data storage status, (2) a not latest data storage status, (3) an invalid data storage status, and (4) an unwritten status. By using the address conversion table and the page status register, at least two data (latest data and past data) can be read for one designated logical address from a host computer.
摘要翻译：在配有闪存的半导体存储器中，使用备份数据。半导体存储器计算机包括地址转换表，用于通过从由读取请求指定的逻辑地址之一指定逻辑地址来检测存储数据的至少两个页面的物理地址。半导体存储器计算机包括用于检测分配给每个页面的一页状态的页面状态寄存器，并且要检测的页面状态包括至少以下四个状态：（1）最新数据存储状态，（2）不是最新的数据存储状态，（3）无效数据存储状态，以及（4）不成文状态。通过使用地址转换表和页面状态寄存器，可以从主机为一个指定的逻辑地址读取至少两个数据（最新数据和过去数据）。

7. 发明授权

US07761655B2 Storage system and method of preventing deterioration of write performance in storage system 失效
标题翻译：防止存储系统中写入性能恶化的存储系统和方法
公开(公告)号：US07761655B2
公开(公告)日：2010-07-20
申请号：US11968218
申请日：2008-01-02
申请人： Nagamasa Mizushima , Shuji Nakamura
发明人： Nagamasa Mizushima , Shuji Nakamura
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0246 , G06F2212/1032 , G06F2212/2022 , G06F2212/7205
摘要： Provided is a storage system capable of inhibiting the deterioration of its write performance. This storage system includes a flash memory, a cache memory, and a controller for controlling the reading, writing and deletion of data of the flash memory and the reading and writing of data of the cache memory, and detecting the generation of a defective block in the flash memory. When the controller detects the generation of a defective block in the flash memory, it migrates prescribed data stored in the flash memory to the cache memory and, even upon receiving from the host computer a command for updating the migrated data, disables the writing of data in the flash memory based on the command.
摘要翻译：提供了能够抑制其写入性能劣化的存储系统。该存储系统包括闪速存储器，高速缓存存储器和用于控制闪速存储器的数据的读取，写入和删除以及高速缓冲存储器的数据的读取和写入的控制器，并且检测有缺陷块的生成闪存。当控制器检测到闪存中的故障块的产生时，它将存储在闪速存储器中的规定数据迁移到高速缓冲存储器，并且即使在从主计算机接收到用于更新迁移的数据的命令时，禁止写入数据在闪存中基于命令。

8. 发明授权

US07694067B2 Memory card 有权
标题翻译：存储卡
公开(公告)号：US07694067B2
公开(公告)日：2010-04-06
申请号：US12015050
申请日：2008-01-16
申请人： Nagamasa Mizushima , Takashi Tsunehiro , Motoyasu Tsunoda , Toshio Tanaka , Kunihiro Katayama , Koichi Kimura , Tomihisa Hatano
发明人： Nagamasa Mizushima , Takashi Tsunehiro , Motoyasu Tsunoda , Toshio Tanaka , Kunihiro Katayama , Koichi Kimura , Tomihisa Hatano
IPC分类号： G06F12/00
CPC分类号： G06K7/0021 , G06F21/602 , G06K7/0047 , G06K19/07732
摘要： A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.
摘要翻译：提供了一种存储装置，其连接用于从主机装置提供的电源和时钟进行操作。存储器件包括外部端子，存储数据的闪存芯片，处理数据的IC芯片; 以及与外部端子，闪存芯片和IC芯片连接的控制器芯片。闪存芯片，IC芯片和控制器芯片是分立芯片。控制器芯片根据主机装置的命令将从主机装置输入的数据写入闪存芯片或IC芯片，并将从闪存芯片或IC芯片读取的数据传送到主机装置。

9. 发明授权

US07571277B2 Semiconductor memory system for flash memory 失效
标题翻译：用于闪存的半导体存储器系统
公开(公告)号：US07571277B2
公开(公告)日：2009-08-04
申请号：US11616932
申请日：2006-12-28
申请人： Nagamasa Mizushima
发明人： Nagamasa Mizushima
IPC分类号： G06F12/00
CPC分类号： G11C16/349 , G06F11/1068 , G11C5/04 , G11C16/04 , G11C16/3495 , G11C29/4401 , G11C29/46 , G11C29/76 , G11C2029/0409 , G11C2029/0411
摘要： Provided is a semiconductor memory system including a plurality of main memory chips and sub-memory chips as alternatives, in which each main memory chip includes a plurality of reserved memory blocks in the same chip as alternatives to an abnormal memory block. When it is detected that the number of the remaining reserved memory blocks unused as blocks to be reassigned has reached a first predetermined value in the main memory chip, the memory blocks in the sub-memory chip starts to be formatted. When the number of the remaining reserved memory blocks unused in the main memory chip reaches a second predetermined value, read/write with respect to the main memory chip is switched to the sub-memory chip, while bypassing the format process for the memory block in the sub-memory chip. Thus, in the semiconductor memory system including a main flash memory, an alternative flash memory, and a write cache memory, the capacity of a RAM for the write cache memory can be reduced.
摘要翻译：提供了一种半导体存储器系统，其包括作为替代的多个主存储器芯片和子存储器芯片，其中每个主存储器芯片包括与替代异常存储器块相同的芯片中的多个保留存储器块。当检测到未被使用的剩余保留存储器块的数量将被重新分配的块已经达到主存储器芯片中的第一预定值时，子存储器芯片中的存储块开始被格式化。当在主存储器芯片中未使用的剩余保留存储器块的数量达到第二预定值时，相对于主存储器芯片的读/写切换到子存储器芯片，同时绕过存储块的格式化处理子存储芯片。因此，在包括主闪速存储器，备用闪存和写入高速缓冲存储器的半导体存储器系统中，可以减少写入高速缓冲存储器的RAM的容量。

10. 发明申请

US20070253251A1 IC MODULE AND CELLULAR PHONE 失效
标题翻译： IC模块和蜂窝电话
公开(公告)号：US20070253251A1
公开(公告)日：2007-11-01
申请号：US11740961
申请日：2007-04-27
申请人： Nagamasa Mizushima , Kunihiro Katayama , Masaharu Ukeda , Yoshinori Mochizuki
发明人： Nagamasa Mizushima , Kunihiro Katayama , Masaharu Ukeda , Yoshinori Mochizuki
IPC分类号： G11C16/04
CPC分类号： G06K19/0723 , G06K19/07 , G06K19/072 , G06Q20/105
摘要： In a SIM card having a flash memory chip, a memory controller chip, and contact/contactless card interfaces, the memory controller chip has a function of executing user authentication of a host equipment, executes processing of data transmitted through the contactless IC card interface (executing reading or writing of data to the flash memory chip) using power supplied from the host equipment to the contact IC card interface, and executes initialization of the flash memory chip between activation of the host equipment and completion of user authentication instructed by the host equipment.
摘要翻译：在具有闪速存储器芯片，存储器控制器芯片和接触/非接触卡接口的SIM卡中，存储器控制器芯片具有执行主机设备的用户认证的功能，执行通过非接触IC卡接口传输的数据的处理（使用从主机设备向接触式IC卡接口提供的电力执行对闪存芯片的数据读取或写入，并且在主机设备激活和主机设备指示的用户认证完成之间执行闪存芯片的初始化。

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