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1. 发明授权

US08088632B2 Elemental analysis method and semiconductor device manufacturing method 有权
标题翻译：元素分析方法和半导体器件制造方法
公开(公告)号：US08088632B2
公开(公告)日：2012-01-03
申请号：US12494977
申请日：2009-06-30
申请人： Satoshi Shibata , Hisako Kamiyanagi , Fumitoshi Kawase , Tetsuyuki Okano
发明人： Satoshi Shibata , Hisako Kamiyanagi , Fumitoshi Kawase , Tetsuyuki Okano
IPC分类号： H01L21/00
CPC分类号： H01L22/20 , H01J2237/2566 , H01J2237/31703 , H01L22/12
摘要： Protons are entered into a substrate to be analyzed at a proton incident angle larger than 0° and smaller 90°. Excited by the entered protons and emitted from the substrate to be analyzed, the characteristic X-ray is measured by an energy dispersive X-ray detector and the like. Impurity elements present in the substrate to be analyzed are identified based on the measured characteristic X-ray. The in-plane distribution in the substrate can be obtained by scanning the proton beam. The in-depth distribution can be obtained by entering protons at different proton incident angles. The elemental analysis method can be applied to semiconductor device manufacturing processes to analyze metal contamination or quantify a conductivity determining impurity element on an inline basis and with a high degree of accuracy.
摘要翻译：质子以大于0°和较小90°的质子入射角进入基底进行分析。由输入的质子激发并从要分析的基板发射，通过能量色散X射线检测器等测量特征X射线。基于所测量的特征X射线识别存在于待分析基板中的杂质元素。可以通过扫描质子束来获得衬底中的面内分布。可以通过在不同的质子入射角进入质子来获得深度分布。元素分析方法可以应用于半导体器件制造工艺，以分析金属污染或者在线性基础上以高准确度量化电导率确定杂质元素。

2. 发明申请

US20100003770A1 ELEMENTAL ANALYSIS METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：元素分析方法和半导体器件制造方法
公开(公告)号：US20100003770A1
公开(公告)日：2010-01-07
申请号：US12494977
申请日：2009-06-30
申请人： Satoshi SHIBATA , Hisako Kamiyanagi , Fumitoshi Kawase , Tetsuyuki Okano
发明人： Satoshi SHIBATA , Hisako Kamiyanagi , Fumitoshi Kawase , Tetsuyuki Okano
IPC分类号： H01L21/66 , G01N23/223 , A61N5/00 , H01J37/08
CPC分类号： H01L22/20 , H01J2237/2566 , H01J2237/31703 , H01L22/12
摘要： Protons are entered into a substrate to be analyzed at a proton incident angle larger than 0° and smaller 90°. Excited by the entered protons and emitted from the substrate to be analyzed, the characteristic X-ray is measured by an energy dispersive X-ray detector and the like. Impurity elements present in the substrate to be analyzed are identified based on the measured characteristic X-ray. The in-plane distribution in the substrate can be obtained by scanning the proton beam. The in-depth distribution can be obtained by entering protons at different proton incident angles. The elemental analysis method can be applied to semiconductor device manufacturing processes to analyze metal contamination or quantify a conductivity determining impurity element on an inline basis and with a high degree of accuracy.
摘要翻译：质子以大于0°和较小90°的质子入射角进入基底进行分析。由输入的质子激发并从要分析的基板发射，通过能量色散X射线检测器等测量特征X射线。基于所测量的特征X射线识别存在于待分析基板中的杂质元素。可以通过扫描质子束来获得衬底中的面内分布。可以通过在不同的质子入射角进入质子来获得深度分布。元素分析方法可以应用于半导体器件制造工艺，以分析金属污染或者在线性基础上以高准确度量化电导率确定杂质元素。

3. 发明授权

US07319061B2 Method for fabricating electronic device 有权
标题翻译：电子设备制造方法
公开(公告)号：US07319061B2
公开(公告)日：2008-01-15
申请号：US11586586
申请日：2006-10-26
申请人： Satoshi Shibata , Fumitoshi Kawase , Hisako Kamiyanagi , Emi Kanazaki
发明人： Satoshi Shibata , Fumitoshi Kawase , Hisako Kamiyanagi , Emi Kanazaki
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.
摘要翻译：在制造包括具有漏极延伸结构的晶体管的电子器件的方法中，预先获得晶体管的栅电极的尺寸和离子注入条件或用于形成漏极延伸结构的热处理条件之间的对应关系。该对应性满足晶体管具有给定的阈值电压。在形成栅电极并测量栅电极的尺寸之后，基于先前获得的对应关系和所测量的栅电极的尺寸来设定用于形成漏极延伸结构的离子注入条件或热处理条件。用于形成漏极延伸结构的离子注入或热处理在已设定的离子注入条件或热处理条件下进行。

4. 发明授权

US07282416B2 Method for fabricating electronic device 有权
标题翻译：电子设备制造方法
公开(公告)号：US07282416B2
公开(公告)日：2007-10-16
申请号：US11241950
申请日：2005-10-04
申请人： Satoshi Shibata , Fumitoshi Kawase , Hisako Kamiyanagi , Emi Kanazaki
发明人： Satoshi Shibata , Fumitoshi Kawase , Hisako Kamiyanagi , Emi Kanazaki
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.
摘要翻译：在制造包括具有漏极延伸结构的晶体管的电子器件的方法中，预先获得晶体管的栅电极的尺寸和离子注入条件或用于形成漏极延伸结构的热处理条件之间的对应关系。该对应性满足晶体管具有给定的阈值电压。在形成栅电极并测量栅电极的尺寸之后，基于先前获得的对应关系和所测量的栅电极的尺寸来设定用于形成漏极延伸结构的离子注入条件或热处理条件。用于形成漏极延伸结构的离子注入或热处理在已设定的离子注入条件或热处理条件下进行。

5. 发明申请

US20070048918A1 Method for fabricating electronic device 有权
公开(公告)号：US20070048918A1
公开(公告)日：2007-03-01
申请号：US11586586
申请日：2006-10-26
申请人： Satoshi Shibata , Fumitoshi Kawase , Hisako Kamiyanagi , Emi Kanazaki
发明人： Satoshi Shibata , Fumitoshi Kawase , Hisako Kamiyanagi , Emi Kanazaki
IPC分类号： H01L21/8234
CPC分类号： H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.

6. 发明申请

US20060079044A1 Method for fabricating electronic device 有权
标题翻译：电子设备制造方法
公开(公告)号：US20060079044A1
公开(公告)日：2006-04-13
申请号：US11241950
申请日：2005-10-04
申请人： Satoshi Shibata , Fumitoshi Kawase , Hisako Kamiyanagi , Emi Kanazaki
发明人： Satoshi Shibata , Fumitoshi Kawase , Hisako Kamiyanagi , Emi Kanazaki
IPC分类号： H01L21/8234
CPC分类号： H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.
摘要翻译：在制造包括具有漏极延伸结构的晶体管的电子器件的方法中，预先获得晶体管的栅电极的尺寸和离子注入条件或用于形成漏极延伸结构的热处理条件之间的对应关系。该对应性满足晶体管具有给定的阈值电压。在形成栅电极并测量栅电极的尺寸之后，基于先前获得的对应关系和所测量的栅电极的尺寸来设定用于形成漏极延伸结构的离子注入条件或热处理条件。用于形成漏极延伸结构的离子注入或热处理在已设定的离子注入条件或热处理条件下进行。

7. 发明申请

US20080128616A1 Resin film evaluation method and method for manufacturing a semiconductor device 失效
标题翻译：树脂膜评价方法及半导体装置的制造方法
公开(公告)号：US20080128616A1
公开(公告)日：2008-06-05
申请号：US11987185
申请日：2007-11-28
申请人： Hisako Kamiyanagi , Satoshi Sibata , Reiki Kaneki , Kohei Miyagawa
发明人： Hisako Kamiyanagi , Satoshi Sibata , Reiki Kaneki , Kohei Miyagawa
IPC分类号： G01N23/00 , H01L21/66
CPC分类号： G01N23/227 , H01L22/14 , H01L22/24 , H01L2924/0002 , H01L2924/00
摘要： In the resin film evaluation method and method for manufacturing a semiconductor device applying the resin film evaluation method of the present invention, first, a substrate having a resin film formed on an insulating film with an opening in which the surface of the insulating film is exposed is irradiated with charged energetic particles. Then, the surface potentials of the substrate surface irradiated with charged energetic particles are measured. Based on the measurements, the difference in surface potential between the resin film and the insulating film exposed in the opening is obtained. Based on the difference in surface potential, a physical quantity such as the resin film residue count obtained after a given treatment is predicted. In this way, the degenerated layer formed on the surface of a resin film due to charged energetic particles such as implantation ions can be evaluated in a simple and highly accurate manner.
摘要翻译：在施加本发明的树脂膜评价方法的半导体装置的树脂膜评价方法和制造方法中，首先，在绝缘膜上形成有绝缘膜的绝缘膜的表面露出的具有树脂膜的基板被带电的能量粒子照射。然后，测量用带电能量粒子照射的基板表面的表面电位。基于这些测量，获得树脂膜和暴露在开口中的绝缘膜之间的表面电位差。基于表面电位的差异，预测在给定处理后获得的树脂膜残留物数量等物理量。以这种方式，可以以简单且高精度的方式评估由于诸如注入离子的带电能量粒子在树脂膜的表面上形成的退化层。

8. 发明授权

US07880141B2 Resin film evaluation method and method for manufacturing a semiconductor device 失效
标题翻译：树脂膜评价方法及半导体装置的制造方法
公开(公告)号：US07880141B2
公开(公告)日：2011-02-01
申请号：US11987185
申请日：2007-11-28
申请人： Hisako Kamiyanagi , Satoshi Sibata , Reiki Kaneki , Kohei Miyagawa
发明人： Hisako Kamiyanagi , Satoshi Sibata , Reiki Kaneki , Kohei Miyagawa
IPC分类号： G01N23/00 , H01L21/66
CPC分类号： G01N23/227 , H01L22/14 , H01L22/24 , H01L2924/0002 , H01L2924/00
摘要： In the resin film evaluation method and method for manufacturing a semiconductor device applying the resin film evaluation method of the present invention, first, a substrate having a resin film formed on an insulating film with an opening in which the surface of the insulating film is exposed is irradiated with charged energetic particles. Then, the surface potentials of the substrate surface irradiated with charged energetic particles are measured. Based on the measurements, the difference in surface potential between the resin film and the insulating film exposed in the opening is obtained. Based on the difference in surface potential, a physical quantity such as the resin film residue count obtained after a given treatment is predicted. In this way, the degenerated layer formed on the surface of a resin film due to charged energetic particles such as implantation ions can be evaluated in a simple and highly accurate manner.
摘要翻译：在施加本发明的树脂膜评价方法的半导体装置的树脂膜评价方法和制造方法中，首先，在绝缘膜上形成有绝缘膜的绝缘膜的表面露出的具有树脂膜的基板被带电的能量粒子照射。然后，测量用带电能量粒子照射的基板表面的表面电位。基于这些测量，获得树脂膜和暴露在开口中的绝缘膜之间的表面电位差。基于表面电位的差异，预测在给定处理后获得的树脂膜残留物数量等物理量。以这种方式，可以以简单且高精度的方式评估由于诸如注入离子的带电能量粒子在树脂膜的表面上形成的退化层。

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