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1. 发明申请

US20080128616A1 Resin film evaluation method and method for manufacturing a semiconductor device 失效
标题翻译：树脂膜评价方法及半导体装置的制造方法
公开(公告)号：US20080128616A1
公开(公告)日：2008-06-05
申请号：US11987185
申请日：2007-11-28
申请人： Hisako Kamiyanagi , Satoshi Sibata , Reiki Kaneki , Kohei Miyagawa
发明人： Hisako Kamiyanagi , Satoshi Sibata , Reiki Kaneki , Kohei Miyagawa
IPC分类号： G01N23/00 , H01L21/66
CPC分类号： G01N23/227 , H01L22/14 , H01L22/24 , H01L2924/0002 , H01L2924/00
摘要： In the resin film evaluation method and method for manufacturing a semiconductor device applying the resin film evaluation method of the present invention, first, a substrate having a resin film formed on an insulating film with an opening in which the surface of the insulating film is exposed is irradiated with charged energetic particles. Then, the surface potentials of the substrate surface irradiated with charged energetic particles are measured. Based on the measurements, the difference in surface potential between the resin film and the insulating film exposed in the opening is obtained. Based on the difference in surface potential, a physical quantity such as the resin film residue count obtained after a given treatment is predicted. In this way, the degenerated layer formed on the surface of a resin film due to charged energetic particles such as implantation ions can be evaluated in a simple and highly accurate manner.
摘要翻译：在施加本发明的树脂膜评价方法的半导体装置的树脂膜评价方法和制造方法中，首先，在绝缘膜上形成有绝缘膜的绝缘膜的表面露出的具有树脂膜的基板被带电的能量粒子照射。然后，测量用带电能量粒子照射的基板表面的表面电位。基于这些测量，获得树脂膜和暴露在开口中的绝缘膜之间的表面电位差。基于表面电位的差异，预测在给定处理后获得的树脂膜残留物数量等物理量。以这种方式，可以以简单且高精度的方式评估由于诸如注入离子的带电能量粒子在树脂膜的表面上形成的退化层。

2. 发明授权

US08269274B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08269274B2
公开(公告)日：2012-09-18
申请号：US12613150
申请日：2009-11-05
申请人： Kohei Miyagawa , Yasushi Kobayashi , Daigo Yamashina
发明人： Kohei Miyagawa , Yasushi Kobayashi , Daigo Yamashina
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/66689
摘要： In a semiconductor substrate of a first conductivity type, first to third drain offset regions of a second conductivity type are formed in that order in a bottom up manner. A body region of the first conductivity type is formed partly in the second drain offset region and partly in the third drain offset region. The second drain offset region has a lower impurity concentration than the first and third drain offset regions. A curvature portion of the body region is located in the second drain offset region.
摘要翻译：在第一导电类型的半导体衬底中，以自下而上的顺序形成第二导电类型的第一至第三漏极偏移区域。第一导电类型的主体区域部分地形成在第二漏极偏移区域中，部分地形成在第三漏极偏移区域中。第二漏极偏移区域具有比第一和第三漏极偏移区域更低的杂质浓度。身体区域的曲率部分位于第二漏极偏移区域中。

3. 发明申请

US20100123194A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100123194A1
公开(公告)日：2010-05-20
申请号：US12613150
申请日：2009-11-05
申请人： Kohei MIYAGAWA , Yasushi Kobayashi , Daigo Yamashina
发明人： Kohei MIYAGAWA , Yasushi Kobayashi , Daigo Yamashina
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/66689
摘要： In a semiconductor substrate of a first conductivity type, first to third drain offset regions of a second conductivity type are formed in that order in a bottom up manner. A body region of the first conductivity type is formed partly in the second drain offset region and partly in the third drain offset region. The second drain offset region has a lower impurity concentration than the first and third drain offset regions. A curvature portion of the body region is located in the second drain offset region.
摘要翻译：在第一导电类型的半导体衬底中，以自下而上的顺序形成第二导电类型的第一至第三漏极偏移区域。第一导电类型的主体区域部分地形成在第二漏极偏移区域中，部分地形成在第三漏极偏移区域中。第二漏极偏移区域具有比第一和第三漏极偏移区域更低的杂质浓度。身体区域的曲率部分位于第二漏极偏移区域中。

4. 发明授权

US07880141B2 Resin film evaluation method and method for manufacturing a semiconductor device 失效
标题翻译：树脂膜评价方法及半导体装置的制造方法
公开(公告)号：US07880141B2
公开(公告)日：2011-02-01
申请号：US11987185
申请日：2007-11-28
申请人： Hisako Kamiyanagi , Satoshi Sibata , Reiki Kaneki , Kohei Miyagawa
发明人： Hisako Kamiyanagi , Satoshi Sibata , Reiki Kaneki , Kohei Miyagawa
IPC分类号： G01N23/00 , H01L21/66
CPC分类号： G01N23/227 , H01L22/14 , H01L22/24 , H01L2924/0002 , H01L2924/00
摘要： In the resin film evaluation method and method for manufacturing a semiconductor device applying the resin film evaluation method of the present invention, first, a substrate having a resin film formed on an insulating film with an opening in which the surface of the insulating film is exposed is irradiated with charged energetic particles. Then, the surface potentials of the substrate surface irradiated with charged energetic particles are measured. Based on the measurements, the difference in surface potential between the resin film and the insulating film exposed in the opening is obtained. Based on the difference in surface potential, a physical quantity such as the resin film residue count obtained after a given treatment is predicted. In this way, the degenerated layer formed on the surface of a resin film due to charged energetic particles such as implantation ions can be evaluated in a simple and highly accurate manner.
摘要翻译：在施加本发明的树脂膜评价方法的半导体装置的树脂膜评价方法和制造方法中，首先，在绝缘膜上形成有绝缘膜的绝缘膜的表面露出的具有树脂膜的基板被带电的能量粒子照射。然后，测量用带电能量粒子照射的基板表面的表面电位。基于这些测量，获得树脂膜和暴露在开口中的绝缘膜之间的表面电位差。基于表面电位的差异，预测在给定处理后获得的树脂膜残留物数量等物理量。以这种方式，可以以简单且高精度的方式评估由于诸如注入离子的带电能量粒子在树脂膜的表面上形成的退化层。

5. 发明申请

US20100187606A1 SEMICONDUCTOR DEVICE THAT INCLUDES LDMOS TRANSISTOR AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件包括LDMOS晶体管及其制造方法
公开(公告)号：US20100187606A1
公开(公告)日：2010-07-29
申请号：US12690766
申请日：2010-01-20
申请人： Yasushi KOBAYASHI , Masaki Inoue , Kohei Miyagawa
发明人： Yasushi KOBAYASHI , Masaki Inoue , Kohei Miyagawa
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/26586 , H01L21/823814 , H01L29/42368 , H01L29/7816
摘要： A manufacturing method of a semiconductor device including an LDMOS transistor includes: a process (a) of forming a first conductive well diffusion layer in the semiconductor substrate; a process (b) of sequentially forming a gate insulator film, a gate conductive film, and a photoresist film on a region on the semiconductor substrate corresponding to the well diffusion layer; a process (c) of performing photolithography to remove a part of the photoresist film formed in a predetermined region, and etching the gate conductive film using a remaining part of the photoresist film as a mask so as to form an opening in the predetermined region; a process (d) of doping second conductive impurity ions using a remaining part of the gate conductive film and the remaining part of the photoresist film as a mask so as to form the body layer; and a process (e) of removing the remaining part of the gate conductive film except a part corresponding to the gate electrode formed based on a part that constitutes a lateral surface of the gate conductive film facing the opening.
摘要翻译：包括LDMOS晶体管的半导体器件的制造方法包括：在半导体衬底中形成第一导电阱扩散层的工艺（a）; 在对应于阱扩散层的半导体衬底上的区域上依次形成栅极绝缘膜，栅极导电膜和光刻胶膜的工艺（b）进行光刻以去除在预定区域中形成的光致抗蚀剂膜的一部分的工艺（c），并且使用剩余部分的光致抗蚀剂膜作为掩模蚀刻栅极导电膜，以便在预定区域中形成开口; 使用栅极导电膜的剩余部分和光刻胶膜的剩余部分作为掩模来掺杂第二导电杂质离子以形成体层的工艺（d）; 以及除了基于构成面对该开口的栅极导电膜的侧面的部分形成的栅极电极以外的部分除去栅极导电膜的剩余部分的工序（e）。

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