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1. 发明授权

US06560692B1 Data processing circuit, microcomputer, and electronic equipment 失效
标题翻译：数据处理电路，微电脑和电子设备
公开(公告)号：US06560692B1
公开(公告)日：2003-05-06
申请号：US08859490
申请日：1997-05-20
申请人： Makoto Kudo , Satoshi Kubota , Yoshiyuki Miyayama , Hisao Sato
发明人： Makoto Kudo , Satoshi Kubota , Yoshiyuki Miyayama , Hisao Sato
IPC分类号： G06F1500
CPC分类号： G06F9/3004 , G06F9/30101 , G06F9/30163 , G06F9/30167 , G06F9/324 , G06F9/355
摘要： The data processing circuit of this invention enables efficient description and execution of processes that act upon the stack pointer, using short instructions. It also enables efficient description of processes that save and restore the contents of registers, increasing the speed of processing of interrupts and subroutine calls and returns. A CPU that uses this data processing circuit comprises a dedicated stack pointer register SP and uses an instruction decoder to decode a group of dedicated stack pointer instructions that specify the SP as an implicit operand. This group of dedicated stack pointer instructions are implemented in hardware by using general-purpose registers, the PC, the SP, an address adder, an ALU, a PC incrementer, internal buses, internal signal lines, and external buses. This group of dedicated stack pointer instructions comprises SP-relative load instructions, stack pointer move instructions, a call instruction, a ret instruction, a sequential push instruction, and a sequential pop instruction.
摘要翻译：本发明的数据处理电路能够使用简单的指令有效地描述和执行作用于堆栈指针的进程。它还能够有效地描述保存和恢复寄存器内容的进程，提高处理中断和子程序调用和返回的速度。使用该数据处理电路的CPU包括专用堆栈指针寄存器SP，并且使用指令解码器将指定SP的一组专用堆栈指针指令解码为隐式操作数。该组专用堆栈指针指令通过使用通用寄存器，PC，SP，地址加法器，ALU，PC增量器，内部总线，内部信号线和外部总线在硬件中实现。该组专用堆栈指针指令包括SP相对负载指令，堆栈指针移动指令，调用指令，ret指令，顺序推送指令和顺序pop指令。

2. 发明授权

US06233596B1 Multiple sum-of-products circuit and its use in electronic equipment and microcomputers 失效
标题翻译：多产品电路及其在电子设备和微型计算机中的应用
公开(公告)号：US06233596B1
公开(公告)日：2001-05-15
申请号：US09066348
申请日：1998-06-05
申请人： Satoshi Kubota , Makoto Kudo , Yoshiyuki Miyayama
发明人： Satoshi Kubota , Makoto Kudo , Yoshiyuki Miyayama
IPC分类号： G06F9302
CPC分类号： G06F9/30014 , G06F7/5443 , G06F9/30036 , G06F9/325 , G06F17/10
摘要： An objective of this invention is a design that improves the memory usage ratio and execution speed of a sum-of-products operation instruction, improves the critical path of sum-of-products operations, and prevents overflows. A sum-of-products operation circuit executes sum-of-products operations a number of times that is specified by number-of-executions information comprised within a sum-of-products operation instruction, under the control of a control circuit. The number of times the sum-of-products operation is to be executed is set into a register, that number is decremented every time one cycle of the sum-of-products operation ends, and the sum-of-products operation instruction ends when the value in the register reaches zero. If an interrupt is received during the execution of a plurality of sum-of-products operations, execution of the sum-of-products operations resumes after the interrupt processing. First and second sum-of-products input data are read at the same time by a single memory access. A 16-bit×16-bit multiplication result is added by a 32-bit adder, and upper 32-bit data is either incremented or decremented when a carry or borrow is generated by a lower 32-bit add.
摘要翻译：本发明的目的是提高产品总和操作指令的存储器使用率和执行速度的设计，改善产品总和操作的关键路径，并防止溢出。产品总和运算电路在控制电路的控制下，对包含在产品总和运算指令内的执行次数信息指定的次数进行乘积运算。要执行产品总和操作的次数被设置为寄存器，每当产品总和操作的一个周期结束时，该数量减少，并且产品总和操作指令结束时寄存器中的值达到零。如果在执行多个产品总和操作期间接收到中断，则在中断处理之后恢复产品总和操作的执行。通过单个存储器访问同时读取第一和第二产品总和输入数据。一个16位×16位相乘结果由32位加法器相加，当32位加法器产生进位或借位时，高位32位数据被递增或递减。

3. 发明授权

US06308258B1 Data processing circuit with target instruction and prefix instruction 有权
标题翻译：具有目标指令和前缀指令的数据处理电路
公开(公告)号：US06308258B1
公开(公告)日：2001-10-23
申请号：US09717152
申请日：2000-11-22
申请人： Satoshi Kubota , Makoto Kudo , Yoshiyuki Miyayama
发明人： Satoshi Kubota , Makoto Kudo , Yoshiyuki Miyayama
IPC分类号： G06F1500
CPC分类号： G06F9/30185 , G06F9/30076 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/30178 , G06F9/30181
摘要： A certain target instruction and a prefix instruction for expanding the function of that target instruction are input to the present data processing circuit. The data processing circuit analyses the thus-input instruction code and performs the processing necessary for the execution of that instruction. The data processing circuit comprises an instruction decoder section, a register file, and an instruction execution section that executes the instruction based on operational details of the instruction analyzed by the instruction decoder section. The instruction decoder section comprises an ext instruction processing section that processed the expansion of immediate data from the prefix instruction.
摘要翻译：将用于扩展该目标指令的功能的某个目标指令和前缀指令输入到本数据处理电路。数据处理电路分析这样输入的指令代码，并执行执行该指令所需的处理。数据处理电路包括指令解码器部分，寄存器文件和指令执行部分，其基于由指令解码器部分分析的指令的操作细节来执行指令。指令译码器部分包括一个ext指令处理部分，它处理来自前缀指令的立即数据的扩展。

4. 发明授权

US6167505A Data processing circuit with target instruction and prefix instruction 失效
标题翻译：具有目标指令和前缀指令的数据处理电路
公开(公告)号：US6167505A
公开(公告)日：2000-12-26
申请号：US768442
申请日：1996-12-18
申请人： Satoshi Kubota , Makoto Kudo , Yoshiyuki Miyayama
发明人： Satoshi Kubota , Makoto Kudo , Yoshiyuki Miyayama
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F15/00
CPC分类号： G06F9/30185 , G06F9/30076 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/30178 , G06F9/30181
摘要： A certain target instruction and a prefix instruction for expanding the function of that target instruction are input to the present data processing circuit. The data processing circuit analyzes the thus-input instruction code and performs the processing necessary for the execution of that instruction. The data processing circuit comprises an instruction decoder section, a register file, and an instruction execution section that executes the instruction based on operational details of the instruction analyzed by the instruction decoder section. The instruction decoder section comprises an ext instruction processing section that processed the expansion of immediate data from the prefix instruction.
摘要翻译：将用于扩展该目标指令的功能的某个目标指令和前缀指令输入到本数据处理电路。数据处理电路分析这样输入的指令代码，并执行执行该指令所需的处理。数据处理电路包括指令解码器部分，寄存器文件和指令执行部分，其基于由指令解码器部分分析的指令的操作细节来执行指令。指令译码器部分包括一个ext指令处理部分，它处理来自前缀指令的立即数据的扩展。

5. 发明授权

US06922795B2 Microcomputer, electronic equipment, and debugging system 失效
标题翻译：微电脑，电子设备和调试系统
公开(公告)号：US06922795B2
公开(公告)日：2005-07-26
申请号：US10700621
申请日：2003-11-05
申请人： Yoshiyuki Miyayama , Makoto Kudo , Yoichi Hijikata
发明人： Yoshiyuki Miyayama , Makoto Kudo , Yoichi Hijikata
IPC分类号： G06F11/22 , G06F11/28 , G06F11/36 , G06F15/78 , G06F11/00
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/3656 , G06F2201/88
摘要： The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer.A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].
摘要翻译：本发明提供一种微型计算机，其能够使用少量终端在大规模生产的芯片上实现实时跟踪，从指定范围内获取跟踪信息，并且与电子设备一起测量执行时间，以及包括这台微机。跟踪信息输出部分（16）将用于实现实时跟踪的跟踪信息输出到四个专用终端。当PC绝对分支发生时，将CPU的指令执行状态信息（DST [2：0]）输出到三个终端和分支目的地的PC值（DPCO），串行连接到一个终端。微型计算机（10）以规定的顺序向DST [2]输出指示轨迹范围或执行时间测量范围的开始和结束的信息。调试工具（20）根据DST [2]中的值确定跟踪范围或执行时间测量范围的开始和结束。

6. 发明申请

US20050102579A1 Microcomputer, electronic equipment, and debugging system 失效
标题翻译：微电脑，电子设备和调试系统
公开(公告)号：US20050102579A1
公开(公告)日：2005-05-12
申请号：US10985901
申请日：2004-11-12
申请人： Yoshiyuki Miyayama , Makoto Kudo , Yoichi Hijikata
发明人： Yoshiyuki Miyayama , Makoto Kudo , Yoichi Hijikata
IPC分类号： G06F11/22 , G06F11/28 , G06F11/36 , G06F15/78 , G06F11/00
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/3656 , G06F2201/88
摘要： The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].
摘要翻译：本发明提供一种微型计算机，其能够使用少量终端在大规模生产的芯片上实现实时跟踪，从指定范围内获取跟踪信息，并且与电子设备一起测量执行时间，以及包括这台微机。跟踪信息输出部分（16）将用于实现实时跟踪的跟踪信息输出到四个专用终端。当PC绝对分支发生时，将CPU的指令执行状态信息（DST [2：0]）输出到三个终端和分支目的地的PC值（DPCO），串行连接到一个终端。微型计算机（10）以规定的顺序向DST [2]输出指示轨迹范围或执行时间测量范围的开始和结束的信息。调试工具（20）根据DST [2]中的值确定跟踪范围或执行时间测量范围的开始和结束。

7. 发明授权

US07065678B2 Microcomputer, electronic equipment, and debugging system 失效
标题翻译：微电脑，电子设备和调试系统
公开(公告)号：US07065678B2
公开(公告)日：2006-06-20
申请号：US10985901
申请日：2004-11-12
申请人： Yoshiyuki Miyayama , Makoto Kudo , Yoichi Hijikata
发明人： Yoshiyuki Miyayama , Makoto Kudo , Yoichi Hijikata
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/3656 , G06F2201/88
摘要： The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer.A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].
摘要翻译：本发明提供一种微型计算机，其能够使用少量终端在大规模生产的芯片上实现实时跟踪，从指定范围内获取跟踪信息，并且与电子设备一起测量执行时间，以及包括这台微机。跟踪信息输出部分（16）将用于实现实时跟踪的跟踪信息输出到四个专用终端。当PC绝对分支发生时，将CPU的指令执行状态信息（DST [2：0]）输出到三个终端和分支目的地的PC值（DPCO），串行连接到一个终端。微型计算机（10）以规定的顺序向DST [2]输出指示轨迹范围或执行时间测量范围的开始和结束的信息。调试工具（20）根据DST [2]中的值确定跟踪范围或执行时间测量范围的开始和结束。

8. 发明授权

US06799157B1 Method for improving pin compatibility in microcomputer emulation equipment 失效
标题翻译：提高微机仿真设备引脚兼容性的方法
公开(公告)号：US06799157B1
公开(公告)日：2004-09-28
申请号：US09532514
申请日：2000-03-21
申请人： Makoto Kudo , Hirofumi Terasawa , Yoshiyuki Miyayama
发明人： Makoto Kudo , Hirofumi Terasawa , Yoshiyuki Miyayama
IPC分类号： G06E760
CPC分类号： G06F17/5022
摘要： An objective is to provide a microcomputer, electronic equipment and emulation method which can realize the optimum circumstance of evaluation while saving the number of terminals. An external bus is shared between external and emulation memories. In the emulation mode, the access of CPU to an internal ROM is switched to the access of CPU to the emulation memory through an external bus. The emulation mode is turned ON or OFF through a mode selection terminal or mode selection register. The emulation memory is controlled by a control signal CNT2 different from a control signal CNT1 which controls the external memory. A memory read signal in CNT2 become active at a timing earlier than that of a memory read signal in CNT1. Thus, the instruction is fetched and decoded within one clock cycle. A mode selection terminal is further provided for selecting a mode of performing the boot from the emulation memory, internal ROM or external memory and a made of selecting OPT mode.
摘要翻译：目的是提供一种微电脑，电子设备和仿真方法，可以在节省终端数量的同时实现最佳的评估环境。外部总线在外部和仿真存储器之间共享。在仿真模式下，CPU对内部ROM的访问通过外部总线切换到CPU对仿真存储器的访问。仿真模式通过模式选择端子或模式选择寄存器打开或关闭。仿真存储器由与控制外部存储器的控制信号CNT1不同的控制信号CNT2控制。 CNT2中的存储器读取信号比在CNT1中的存储器读取信号的时间早一个时间被激活。因此，指令在一个时钟周期内获取和解码。还提供一种模式选择终端，用于从仿真存储器，内部ROM或外部存储器中选择执行引导的模式，并且选择OPT模式。

9. 发明授权

US06665821B1 Microcomputer, electronic equipment, and debugging system 有权
标题翻译：微电脑，电子设备和调试系统
公开(公告)号：US06665821B1
公开(公告)日：2003-12-16
申请号：US09424718
申请日：2000-02-04
申请人： Yoshiyuki Miyayama , Makoto Kudo , Yoichi Hijikata
发明人： Yoshiyuki Miyayama , Makoto Kudo , Yoichi Hijikata
IPC分类号： G06F1100
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/3656 , G06F2201/88
摘要： The present invention provides a microcomputer that makes, it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].
摘要翻译：本发明提供一种微型计算机，其能够使用少量终端在批量生产的芯片上实现实时跟踪，从指定的范围内获取跟踪信息，并且与电子设备和调试系统一起测量执行时间轨迹信息输出部分（16）将用于实现实时跟踪的跟踪信息输出到四个专用终端。当PC绝对分支发生时，将CPU的指令执行状态信息（DST [2：0]）输出到三个终端和分支目的地的PC值（DPCO），串行连接到一个终端。微型计算机（10）以规定的顺序向DST [2]输出指示轨迹范围或执行时间测量范围的开始和结束的信息。调试工具（20）根据DST [2]中的值确定跟踪范围或执行时间测量范围的开始和结束。

10. 发明授权

US07487333B2 High-performance, superscalar-based computer system with out-of-order instruction execution 失效
公开(公告)号：US07487333B2
公开(公告)日：2009-02-03
申请号：US10700485
申请日：2003-11-05
申请人： Le-Trong Nguyen , Derek J Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H Trang
发明人： Le-Trong Nguyen , Derek J Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H Trang
IPC分类号： G06F9/302 , G06F9/38 , G06F9/40
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

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