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1. 发明授权

US08482961B2 Semiconductor device and its manufacturing method 失效
公开(公告)号：US08482961B2
公开(公告)日：2013-07-09
申请号：US13456195
申请日：2012-04-25
申请人： Satoru Hanzawa , Fumihiko Nitta , Nozomu Matsuzaki , Toshihiro Tanaka
发明人： Satoru Hanzawa , Fumihiko Nitta , Nozomu Matsuzaki , Toshihiro Tanaka
IPC分类号： G11C11/00
CPC分类号： G11C5/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/74 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

2. 发明申请

US20120268981A1 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120268981A1
公开(公告)日：2012-10-25
申请号：US13456195
申请日：2012-04-25
申请人： SATORU HANZAWA , Fumihiko Nitta , Nozomu Matsuzaki , Toshihiro Tanaka
发明人： SATORU HANZAWA , Fumihiko Nitta , Nozomu Matsuzaki , Toshihiro Tanaka
IPC分类号： G11C11/21
CPC分类号： G11C5/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/74 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.
摘要翻译：在包括由可变电阻器使用存储元件的存储器单元和选择晶体管形成的存储单元阵列的半导体器件中，缓冲单元布置在读出放大器和存储单元阵列之间以及字驱动器和存储单元阵列之间。存储单元中的电阻存储元件通过形成在电阻存储元件上方的触点连接到位线。同时，在缓冲单元中，电阻性存储元件之上不形成接触，并且在处理存储单元中的接触时保持被绝缘体覆盖的状态。通过这种处理方法，可以避免在电阻存储元件中使用的硫族化物膜的曝光和升华。

3. 发明授权

US08179739B2 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US08179739B2
公开(公告)日：2012-05-15
申请号：US12672685
申请日：2007-08-10
申请人： Satoru Hanzawa , Fumihiko Nitta , Nozomu Matsuzaki , Toshihiro Tanaka
发明人： Satoru Hanzawa , Fumihiko Nitta , Nozomu Matsuzaki , Toshihiro Tanaka
IPC分类号： G11C8/00
CPC分类号： G11C5/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/74 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.
摘要翻译：一种能够制造半导体器件的技术，而不会在涉及包括由可变电阻器和选择晶体管（CT）使用存储元件（RE）的存储器单元形成的存储单元阵列的相变存储器的制造设备中产生污染。缓冲单元布置在读出放大器（SA）和存储单元阵列（MCA）之间以及字驱动器（WDB）和存储单元阵列之间。缓冲单元由与存储单元相同的电阻存储元件（RE）和选择晶体管（CT）形成。存储单元中的电阻存储元件通过形成在电阻存储元件上方的触点连接到位线。同时，在缓冲单元中，电阻性存储元件之上不形成接触，并且在处理存储单元中的接触时保持被绝缘体覆盖的状态。通过这种处理方法，可以避免在电阻存储元件中使用的硫族化物膜的曝光和升华。

4. 发明申请

US20110211390A1 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110211390A1
公开(公告)日：2011-09-01
申请号：US12672685
申请日：2007-08-10
申请人： Satoru Hanzawa , Fumihiko Nitta , Nozomu Matsuzaki , Toshihiro Tanaka
发明人： Satoru Hanzawa , Fumihiko Nitta , Nozomu Matsuzaki , Toshihiro Tanaka
IPC分类号： G11C11/00 , H01L21/8239
CPC分类号： G11C5/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/74 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.
摘要翻译：一种能够制造半导体器件的技术，而不会在涉及包括由可变电阻器和选择晶体管（CT）使用存储元件（RE）的存储器单元形成的存储单元阵列的相变存储器的制造设备中产生污染。缓冲单元布置在读出放大器（SA）和存储单元阵列（MCA）之间以及字驱动器（WDB）和存储单元阵列之间。缓冲单元由与存储单元相同的电阻存储元件（RE）和选择晶体管（CT）形成。存储单元中的电阻存储元件通过形成在电阻存储元件上方的触点连接到位线。同时，在缓冲单元中，电阻性存储元件之上不形成接触，并且在处理存储单元中的接触时保持被绝缘体覆盖的状态。通过这种处理方法，可以避免在电阻存储元件中使用的硫族化物膜的曝光和升华。

5. 发明申请

US20060220100A1 Semicondudctor device 有权
标题翻译：半导体器件
公开(公告)号：US20060220100A1
公开(公告)日：2006-10-05
申请号：US11415129
申请日：2006-05-02
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

6. 发明申请

US20050258474A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050258474A1
公开(公告)日：2005-11-24
申请号：US10484578
申请日：2002-07-22
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L29/423 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

7. 发明授权

US06459619B1 Non-volatile semiconductor memory device for selectively re-checking word lines 有权
标题翻译：用于选择性地重新检查字线的非易失性半导体存储器件
公开(公告)号：US06459619B1
公开(公告)日：2002-10-01
申请号：US09986081
申请日：2001-11-07
申请人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
发明人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C8/08 , G11C16/12 , G11C16/3404
摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for-each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.
摘要翻译：一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。为每个字线提供字锁存电路，并且每个存储器单元的阈值电压被管理在所选存储器块中的每个字线。每个字锁存电路由多个字线共享，以便减少所需的芯片面积。为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

8. 发明授权

US06711061B2 Non-volatile semiconductor memory device for selectively re-checking word lines 有权
标题翻译：用于选择性地重新检查字线的非易失性半导体存储器件
公开(公告)号：US06711061B2
公开(公告)日：2004-03-23
申请号：US10223488
申请日：2002-08-20
申请人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
发明人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C8/08 , G11C16/12 , G11C16/3404
摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.
摘要翻译：一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。为每个字线提供字锁存电路，并且在所选择的存储器块中为每个字线管理每个存储器单元的阈值电压。每个字锁存电路由多个字线共享，以便减少所需的芯片面积。为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

9. 发明授权

US08017986B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08017986B2
公开(公告)日：2011-09-13
申请号：US12718111
申请日：2010-03-05
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

10. 发明授权

US07414283B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07414283B2
公开(公告)日：2008-08-19
申请号：US11415129
申请日：2006-05-02
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

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