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1. 发明授权

US08643410B1 System for compensating for variations in clock signal frequency 有权
标题翻译：用于补偿时钟信号频率变化的系统
公开(公告)号：US08643410B1
公开(公告)日：2014-02-04
申请号：US13602199
申请日：2012-09-02
申请人： Prashant Bhargava , Mohit Arora , James R. Feddeler , Martin Mienkina
发明人： Prashant Bhargava , Mohit Arora , James R. Feddeler , Martin Mienkina
IPC分类号： H03K9/08
CPC分类号： G04F10/04 , H03L7/00
摘要： A system for compensating for variations in the frequency of an input clock signal having a first frequency includes a coarse counter that receives the input clock signal, counts a predetermined number of clock pulses of the input clock signal, and generates a coarse compensated clock signal having a second frequency. A first compensation module adjusts a clock pulse of the input clock signal based on a coarse compensation value. A residual period adjustment module accumulates a fine compensation value for each clock pulse of the coarse compensated clock signal. A fine counter operates at a third frequency of a fine clock signal, receives an adjusted delay value based on the accumulated fine compensation value, counts a number of fine clock pulses in each clock pulse of the coarse compensated clock signal, and generates a fine compensated clock signal having the second frequency.
摘要翻译：用于补偿具有第一频率的输入时钟信号的频率变化的系统包括接收输入时钟信号的粗计数器，对输入时钟信号的预定数量的时钟脉冲进行计数，并产生具有第二个频率。第一补偿模块基于粗略的补偿值调整输入时钟信号的时钟脉冲。残余周期调整模块对粗补偿时钟信号的每个时钟脉冲累积精细补偿值。精细计数器以精细时钟信号的第三频率工作，基于累积的精细补偿值接收经调整的延迟值，对粗略补偿时钟信号的每个时钟脉冲中的精细时钟脉冲数进行计数，并产生精细补偿时钟信号具有第二频率。

2. 发明授权

US09197231B1 Systems and methods for data conversion 有权
标题翻译：用于数据转换的系统和方法
公开(公告)号：US09197231B1
公开(公告)日：2015-11-24
申请号：US14266193
申请日：2014-04-30
申请人： James R. Feddeler , Michael T. Berens
发明人： James R. Feddeler , Michael T. Berens
IPC分类号： H03M1/12 , H03M1/06 , H03M1/38 , H03M1/40 , H03M1/46
CPC分类号： H03M1/468 , H03M1/0639 , H03M1/0675 , H03M1/069 , H03M1/12 , H03M1/38 , H03M1/40 , H03M1/403 , H03M1/46
摘要： Systems and methods for electronically converting an analog signal to a digital signal are disclosed. The systems and methods may include, for a first bit value, setting a first conversion value to include a first offset; using the output of a first comparison, setting a second conversion value; and if the first bit value has a predetermined relationship to the first offset bit value, removing the first offset from the second conversion value, and, using the output of a second comparison, setting a third conversion value.
摘要翻译：公开了将模拟信号电转换为数字信号的系统和方法。对于第一位值，系统和方法可以包括设置第一转换值以包括第一偏移量; 使用第一比较的输出，设置第二转换值; 并且如果所述第一比特值与所述第一偏移比特值具有预定关系，则从所述第二转换值中移除所述第一偏移量，并且使用所述第二比较的输出来设置第三转换值。

3. 发明授权

US08477052B2 Method and apparatus for self-test of successive approximation register (SAR) A/D converter 有权
公开(公告)号：US08477052B2
公开(公告)日：2013-07-02
申请号：US13079818
申请日：2011-04-05
申请人： Sanjoy K. Dey , Michael T. Berens , James R. Feddeler , Vikram Varma
发明人： Sanjoy K. Dey , Michael T. Berens , James R. Feddeler , Vikram Varma
IPC分类号： H03M1/10
CPC分类号： H03M1/1071 , H03M1/109 , H03M1/468
摘要： A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

4. 发明申请

US20120256774A1 METHOD AND APPARATUS FOR SELF-TEST OF SUCCESSIVE APPROXIMATION REGISTER (SAR) A/D CONVERTER 有权
标题翻译：自适应寄存器（SAR）A / D转换器自检的方法和装置
公开(公告)号：US20120256774A1
公开(公告)日：2012-10-11
申请号：US13079818
申请日：2011-04-05
申请人： Sanjoy K. Dey , Michael T. Berens , James R. Feddeler , Vikram Varma
发明人： Sanjoy K. Dey , Michael T. Berens , James R. Feddeler , Vikram Varma
IPC分类号： H03M1/10
CPC分类号： H03M1/1071 , H03M1/109 , H03M1/468
摘要： A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.
摘要翻译：单端SAR ADC包括一个额外的电容器，一个自检引擎，以及对采样和保持条件的独立控制，可以对ADC进行快速准确的测试。

5. 发明申请

US20100079325A1 DATA CONVERSION CIRCUITRY AND METHOD THEREFOR 有权
公开(公告)号：US20100079325A1
公开(公告)日：2010-04-01
申请号：US12242077
申请日：2008-09-30
申请人： Michael T. Berens , James R. Feddeler
发明人： Michael T. Berens , James R. Feddeler
IPC分类号： G01B11/00
CPC分类号： H03M1/007 , H03M1/1038 , H03M1/46 , H03M1/468 , H03M1/804 , H03M1/808
摘要： A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

6. 发明授权

US5546588A Method and apparatus for preventing a data processing system from entering a non-recoverable state 失效
标题翻译：防止数据处理系统进入不可恢复状态的方法和装置
公开(公告)号：US5546588A
公开(公告)日：1996-08-13
申请号：US350396
申请日：1994-12-05
申请人： Vincent B. Deems , Gregory A. Racino , James R. Feddeler , Victor E. Shiff
发明人： Vincent B. Deems , Gregory A. Racino , James R. Feddeler , Victor E. Shiff
IPC分类号： G06F9/30 , G06F9/00
CPC分类号： G06F9/30083
摘要： A method and apparatus for preventing a data processing system (10) from entering a non-recoverable state. In one form, the present invention uses a pin (40) to indicate whether or not the execution of a non-recoverable instruction is legal. If the pin indicates that the execution of the instruction is legal, then the instruction is executed and the data processing system (10) is placed into a state that requires an external stimulus in order to recover. If the pin indicates that the execution of the instruction is illegal, then the instruction is not permitted to place the data processing system (10) into a state that requires an external stimulus in order to recover. Instead, an internal recovery mechanism is provided which returns the data processing system (10) to normal processing.
摘要翻译：一种用于防止数据处理系统（10）进入不可恢复状态的方法和装置。在一种形式中，本发明使用销（40）来指示不可恢复指令的执行是否合法。如果引脚指示指令的执行是合法的，则执行指令，并且数据处理系统（10）被置于需要外部刺激以恢复的状态。如果引脚指示执行指令是非法的，则不允许指令将数据处理系统（10）置于需要外部刺激的状态以便恢复。而是提供一种将数据处理系统（10）返回到正常处理的内部恢复机制。

7. 发明申请

US20130249723A1 METHOD AND APPARATUS FOR SELF-TEST OF SUCCESSIVE APPROXIMATION REGISTER (SAR) A/D CONVERTER 有权
标题翻译：自适应寄存器（SAR）A / D转换器自检的方法和装置
公开(公告)号：US20130249723A1
公开(公告)日：2013-09-26
申请号：US13901590
申请日：2013-05-24
申请人： Sanjoy K. Dey , Michael T. Berens , James R. Feddeler , Vikram Varma
发明人： Sanjoy K. Dey , Michael T. Berens , James R. Feddeler , Vikram Varma
IPC分类号： H03M1/10
CPC分类号： H03M1/1071 , H03M1/109 , H03M1/468
摘要： A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.
摘要翻译：单端SAR ADC包括一个额外的电容器，一个自检引擎，以及对采样和保持条件的独立控制，可以对ADC进行快速准确的测试。

8. 发明申请

US20100320997A1 METHOD AND CIRCUIT FOR MEASURING QUIESCENT CURRENT 有权
标题翻译：用于测量电流的方法和电路
公开(公告)号：US20100320997A1
公开(公告)日：2010-12-23
申请号：US12487798
申请日：2009-06-19
申请人： Dale J. McQuirk , Michael T. Berens , James R. Feddeler
发明人： Dale J. McQuirk , Michael T. Berens , James R. Feddeler
IPC分类号： G01R19/00
CPC分类号： G01R31/3008
摘要： A measurement circuit and method for measuring a quiescent current of a circuit under test are provided. The measurement circuit comprises: a comparator having a first input terminal for receiving a reference voltage, a second input terminal coupled to the circuit under test, and an output terminal; a current source having a first terminal coupled to a first power supply voltage terminal, and a second terminal for providing a current to the circuit under test; a first switch having a first terminal coupled to the second terminal of the current source, a second terminal coupled to the circuit under test, and a control terminal coupled to the output terminal of the comparator; and a first counter having a first input terminal coupled to the output terminal of the comparator, a second input terminal for receiving a clock signal, and an output terminal for providing a first counter value associated with the quiescent current.
摘要翻译：提供了一种用于测量被测电路的静态电流的测量电路和方法。测量电路包括：比较器，具有用于接收参考电压的第一输入端子，耦合到被测电路的第二输入端子和输出端子; 具有耦合到第一电源电压端子的第一端子的电流源和用于向被测电路提供电流的第二端子; 第一开关，其具有耦合到电流源的第二端子的第一端子，耦合到被测电路的第二端子和耦合到比较器的输出端子的控制端子; 以及第一计数器，具有耦合到比较器的输出端的第一输入端，用于接收时钟信号的第二输入端，以及用于提供与静态电流相关联的第一计数值的输出端。

9. 发明申请

US20100079319A1 DATA CONVERSION CIRCUITRY AND METHOD THEREFOR 有权
公开(公告)号：US20100079319A1
公开(公告)日：2010-04-01
申请号：US12242124
申请日：2008-09-30
申请人： Michael T. Berens , James R. Feddeler
发明人： Michael T. Berens , James R. Feddeler
IPC分类号： H03M1/10
CPC分类号： H03M1/1038 , H03M1/468 , H03M1/68 , H03M1/804
摘要： A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

10. 发明授权

US06661264B2 Releasing functional blocks in response to a determination of a supply voltage predetermined level and a logic predetermined initial state 有权
标题翻译：响应于确定电源电压预定电平和逻辑预定初始状态来释放功能块
公开(公告)号：US06661264B2
公开(公告)日：2003-12-09
申请号：US09967180
申请日：2001-09-28
申请人： Nathan Y. Moyal , James R. Feddeler , Michael Kent , Raha K. Prasun
发明人： Nathan Y. Moyal , James R. Feddeler , Michael Kent , Raha K. Prasun
IPC分类号： H03K1722
CPC分类号： H03K17/223
摘要： An integrated circuit may be initialized by determining that the supply voltage is ramping up and resetting logic in the integrated circuit to a predetermined initial state using a reset signal. After the logic is determined to be in its initial state and the supply voltage is established, the reset signal may be latched off.
摘要翻译：可以通过使用复位信号确定电源电压正在上升并将集成电路中的逻辑复位到预定的初始状态来初始化集成电路。在确定逻辑处于其初始状态并且建立电源电压之后，可以锁存复位信号。

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