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1. 发明申请

US20070113022A1 Missing store operation accelerator 有权
标题翻译：缺少商店操作加速器
公开(公告)号：US20070113022A1
公开(公告)日：2007-05-17
申请号：US11271056
申请日：2005-11-12
申请人： Santosh Abraham , Lawrence Spracklen , Yuan Chou
发明人： Santosh Abraham , Lawrence Spracklen , Yuan Chou
IPC分类号： G06F13/28
CPC分类号： G06F12/0859
摘要： Maintaining a cache of indications of exclusively-owned coherence state for memory space units (e.g., cache line) allows reduction, if not elimination, of delay from missing store operations. In addition, the indications are maintained without corresponding data of the memory space unit, thus allowing representation of a large memory space with a relatively small missing store operation accelerator. With the missing store operation accelerator, a store operation, which misses in low-latency memory (e.g., L1 or L2 cache), proceeds as if the targeted memory space unit resides in the low-latency memory, if indicated in the missing store operation accelerator. When a store operation misses in low-latency memory and hits in the accelerator, a positive acknowledgement is transmitted to the writing processing unit allowing the store operation to proceed. An entry is allocated for the store operation, the store data is written into the allocated entry, and the target of the store operation is requested from memory. When a copy of the data at the requested memory space unit returns, the rest of the allocated entry is updated.
摘要翻译：维护用于存储器空间单元（例如，高速缓存行）的专有相干状态的指示的缓存允许减少（如果不是消除）缺失存储操作的延迟。此外，在没有存储器空间单元的相应数据的情况下维持指示，从而允许用相对较小的缺少存储操作加速器来表示大的存储空间。在缺少存储操作加速器的情况下，在低延迟存储器（例如L1或L2高速缓存）中丢失的存储操作如同目标存储器空间单元驻留在低延迟存储器中那样进行，如果在缺少的存储操作加速器。当存储操作在低延迟存储器中错过并且在加速器中点击时，肯定确认被发送到写入处理单元，从而允许存储操作继续进行。为存储操作分配条目，将存储数据写入分配的条目，并且从存储器请求存储操作的目标。当所请求的存储器空间单元上的数据的副本返回时，所分配的条目的其余部分被更新。

2. 发明申请

US20050086453A1 Method and apparatus for alleviating register window size constraints 有权
标题翻译：缓解寄存器窗口大小约束的方法和装置
公开(公告)号：US20050086453A1
公开(公告)日：2005-04-21
申请号：US10654256
申请日：2003-09-03
申请人： Lawrence Spracklen , Stevan Vlaovic , Steven Hart
发明人： Lawrence Spracklen , Stevan Vlaovic , Steven Hart
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/30127 , G06F9/30043 , G06F9/30076 , G06F9/30101
摘要： A method and apparatus provides the capability for a single function to safely use multiple register windows within the same function, with minimal additional support from the operating system, by specifying a new window pointer, the “Effective Current Window Pointer” (ECWP), to be used in conjunction with the prior art window pointer. According to the present invention, the new window pointer ECWP can be used to override the prior art window pointer in dictating from which register window the operands stipulated by the instructions to be executed are sourced/sinked. Consequently, using the method and apparatus of the invention, the number of spills to memory is reduced, the number of instructions required is decreased, resources are used more efficiently, and costly dependency problems and RAW (read-after-write) stalls are prevented.
摘要翻译：一种方法和装置通过指定一个新的窗口指针“有效当前窗口指针”（ECWP），为单个功能提供了在相同功能中安全地使用多个寄存器窗口的能力，同时通过操作系统的最小额外的支持，与现有技术的窗口指针结合使用。根据本发明，可以使用新的窗口指针ECWP来覆盖现有技术的窗口指针，从而从哪个寄存器窗口指定要执行的指令规定的操作数来源/汇入。因此，使用本发明的方法和装置，减少了对存储器的溢出次数，减少了所需指令的数量，更有效地使用资源，并且防止了昂贵的依赖问题和RAW（写后读取）停止。

3. 发明授权

US08553876B1 High performance cryptography on chip multithreading processors 有权
标题翻译：片上多线程处理器的高性能加密技术
公开(公告)号：US08553876B1
公开(公告)日：2013-10-08
申请号：US11877167
申请日：2007-10-23
申请人： Lawrence Spracklen
发明人： Lawrence Spracklen
IPC分类号： G06F21/00
CPC分类号： H04L9/0625 , G06F21/72 , H04L2209/12
摘要： Improved performance of a chip multithreading (CMT) processor during processing of a cipher is disclosed. The chip multithreading processor may be located on a chip multithreading processor chip that includes a processor cache. The selection of a cipher is received. The cipher is processed by executing a plurality of cryptographic operations on the chip multithreading processor. Lookup tables used during the execution of the plurality of cryptographic operations are determined. The size of at least one of the lookup tables may be increased, such that the at least one lookup table is able to be stored in a processor cache located on the chip multithreading processor chip. Further adjustments may be made to the size of one or more lookup tables depending on the cipher selected, other operations executing on the chip multithreading processor, or both.
摘要翻译：公开了处理密码期间芯片多线程（CMT）处理器性能的改进。芯片多线程处理器可以位于包括处理器高速缓存的芯片多线程处理器芯片上。接收到密码的选择。通过在芯片多线程处理器上执行多个密码操作来处理密码。确定在执行多个密码操作期间使用的查找表。可以增加至少一个查找表的大小，使得至少一个查找表能够存储在位于芯片多线程处理器芯片上的处理器高速缓存中。可以根据所选择的密码，在芯片多线程处理器上执行的其他操作或两者来进一步调整一个或多个查找表的大小。

4. 发明授权

US09189758B2 Administration of a network 有权
标题翻译：管理网络
公开(公告)号：US09189758B2
公开(公告)日：2015-11-17
申请号：US13594633
申请日：2012-08-24
申请人： Vijayaraghavan Soundararajan , Emre Celebi , Harish Muppalla , Lawrence Spracklen
发明人： Vijayaraghavan Soundararajan , Emre Celebi , Harish Muppalla , Lawrence Spracklen
IPC分类号： G06Q10/06 , H04L12/26 , H04L12/24 , G06Q50/00
CPC分类号： H04L51/32 , G06Q10/06 , G06Q50/01 , H04L41/0893 , H04L43/08
摘要： A computer-implemented method to facilitate administration of a network of members. Members of a network are provided with access to a shared message stream such that the members of the network are able to monitor messages generated by other members of the network posted to the shared message stream, wherein at least some of the messages are indicative of operational conditions of particular other members which generated the messages. Responsive to a first member of the network identifying a specific operational condition of the first member, the shared message stream is monitored for a message related to the specific operational condition. Provided the shared message stream includes a message related to the specific operational condition identified by the first member, an association of the message with an indication that the first member identifies with the specific operational condition is established, wherein the first member is configured to establish the association.
摘要翻译：一种便于管理成员网络的计算机实现的方法。向网络的成员提供对共享消息流的访问，使得网络的成员能够监视由发布到共享消息流的网络的其他成员生成的消息，其中至少一些消息指示操作生成消息的特定其他成员的条件。响应于识别第一成员的特定操作条件的网络的第一成员，监视共享消息流以获得与特定操作条件相关的消息。如果共享消息流包括与由第一成员识别的特定操作条件有关的消息，则建立消息与第一成员以特定操作条件标识的指示的关联，其中第一成员被配置为建立协会。

5. 发明申请

US20110091035A1 HARDWARE KASUMI CYPHER WITH HYBRID SOFTWARE INTERFACE 审中-公开
标题翻译：具有混合软件接口的硬件KASUMI CYPHER
公开(公告)号：US20110091035A1
公开(公告)日：2011-04-21
申请号：US12582299
申请日：2009-10-20
申请人： Lawrence Spracklen , Farnad Sajjadian , Christopher H. Olson , Sanjay Patel
发明人： Lawrence Spracklen , Farnad Sajjadian , Christopher H. Olson , Sanjay Patel
IPC分类号： H04L9/18
CPC分类号： H04L9/0625 , H04L2209/12 , H04L2209/20 , H04L2209/80 , H04W12/02 , H04W12/10
摘要： A system including a memory; a software interface, operatively connected to the memory, and configured to generate a modified version of a confidentially key (CKey), and a modified version of an integrity key (IKey); and a Kasumi engine having a hardware implementation of a Kasumi cipher and configured to load the modified version of the CKey from the memory to perform a confidentiality function, and to load the modified version of the IKey from memory to perform an integrity function.
摘要翻译：包括存储器的系统; 软件接口，可操作地连接到存储器，并被配置为生成保密键（CKey）的修改版本和完整性密钥（IKey）的修改版本; 以及具有Kasumi密码的硬件实现的Kasumi引擎，并且被配置为从存储器加载CKey的修改版本以执行机密功能，并且从存储器加载IKey的修改版本以执行完整性功能。

6. 发明授权

US07003653B2 Method for rapid interpretation of results returned by a parallel compare instruction 有权
标题翻译：用于快速解释并行比较指令返回的结果的方法
公开(公告)号：US07003653B2
公开(公告)日：2006-02-21
申请号：US10277639
申请日：2002-10-21
申请人： Lawrence Spracklen
发明人： Lawrence Spracklen
IPC分类号： G06F9/305
CPC分类号： G06F9/30021 , G06F9/30018 , G06F9/30036 , G06F9/3885 , G06F9/3887
摘要： A method for rapidly mapping a bitmask returned by a Single Instruction Multiple Data (SIMD) computer compare instruction is provided. A user supplied partitioned mapping variable includes multiple mapping elements. Each of the multiple mapping elements is applied to the inputs of a different one of multiple digital multiplexers. The bitmask returned by the SIMD compare instruction is applied to the selects or all of the multiple digital multiplexers. Each multiplexer outputs one bit, as selected by the bitmask, from the respective mapping element applied to each multiplexer. The one bit outputs are accumulated in a mapped output variable as a mapped bitmask.
摘要翻译：提供了一种快速映射单指令多数据（SIMD）计算机比较指令返回的位掩码的方法。用户提供的分区映射变量包含多个映射元素。多个映射元素中的每一个被应用于多个数字多路复用器中的不同的一个的输入。由SIMD比较指令返回的位掩码应用于多个数字多路复用器的选择或全部。每个复用器从应用于每个多路复用器的相应映射元件输出由位掩码选择的一个位。一位输出在映射的输出变量中作为映射位掩码累积。

7. 发明授权

US09111241B2 Creation of a social network of members of a virtualization infrastructure 有权
标题翻译：创建虚拟化基础架构成员的社交网络
公开(公告)号：US09111241B2
公开(公告)日：2015-08-18
申请号：US13594605
申请日：2012-08-24
申请人： Vijayaraghavan Soundararajan , Emre Celebi , Harish Muppalla , Lawrence Spracklen
发明人： Vijayaraghavan Soundararajan , Emre Celebi , Harish Muppalla , Lawrence Spracklen
IPC分类号： G06F15/16 , G06Q10/06 , H04L12/26 , H04L12/24 , G06Q50/00
CPC分类号： H04L51/32 , G06Q10/06 , G06Q50/01 , H04L41/0893 , H04L43/08
摘要： A computer-implemented method for creating a social network of members of a virtualization infrastructure. At a virtualization infrastructure manager, at least a portion of the members of the virtualization infrastructure are identified. Parent/child relationships of identified members of the virtualization infrastructure are identified. A social network of the identified members of the virtualization infrastructure is generated based on the identified parent/child relationships. Affiliation relationships between parent members and child members of the virtualization infrastructure are established, wherein the child members can access shared message streams corresponding to the parent members, such that a child member can establish an association of a message from a shared message stream with an indication that the child member identifies with content of the message.
摘要翻译：用于创建虚拟化基础设施的成员的社交网络的计算机实现的方法。在虚拟化基础架构管理器中，至少部分虚拟化基础设施的成员被识别。识别虚拟化基础设施的已识别成员的父/子关系。基于所识别的父/子关系生成所识别的虚拟化基础设施成员的社交网络。建立了虚拟化基础设施的父成员和子成员之间的关联关系，其中子成员可以访问与父成员相对应的共享消息流，使得子成员可以建立来自共享消息流的消息与指示的关联子成员用消息的内容标识。

8. 发明授权

US08793439B2 Accelerating memory operations using virtualization information 有权
标题翻译：使用虚拟化信息加速内存操作
公开(公告)号：US08793439B2
公开(公告)日：2014-07-29
申请号：US12726655
申请日：2010-03-18
申请人： Lawrence Spracklen
发明人： Lawrence Spracklen
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/08
CPC分类号： G06F12/0815 , G06F9/45533 , G06F12/0817 , G06F12/0831 , G06F12/0837 , G06F2009/45583
摘要： A method of accelerating memory operations using virtualization information includes executing a hypervisor on hardware resources of a computing system. A plurality of domains are created under the control of the hypervisor. Each domain is allocated memory resources that include accessible memory space that is exclusively accessible by that domain. Each domain is allocated one or more processor resources. The hypervisor identifies domain layout information that includes a boundary of accessible memory space of each domain. The hypervisor provides the domain layout information to each processor resource. Each processor resource is configured to implement, on a per domain basis, a restricted coherency protocol based on the domain layout information. The restricted coherency protocol bypasses, relative to the domain, downstream caches when a cache line falls within the accessible memory space of that domain.
摘要翻译：使用虚拟化信息加速存储器操作的方法包括在计算系统的硬件资源上执行管理程序。在管理程序的控制下创建多个域。每个域都分配了内存资源，其中包含该域唯一可访问的可访问内存空间。每个域被分配一个或多个处理器资源。管理程序识别包括每个域的可访问内存空间边界的域布局信息。管理程序为每个处理器资源提供域布局信息。每个处理器资源被配置为基于域布局信息在每个域的基础上实现受限的一致性协议。当高速缓存行落在该域的可访问存储器空间内时，受限的一致性协议相对于域绕过下游缓存。

9. 发明授权

US08583902B2 Instruction support for performing montgomery multiplication 有权
标题翻译：指令支持执行montgomery乘法
公开(公告)号：US08583902B2
公开(公告)日：2013-11-12
申请号：US12776172
申请日：2010-05-07
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence Spracklen , Nils Gura
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence Spracklen , Nils Gura
IPC分类号： G06F9/30
CPC分类号： G06F7/728 , G06F9/30014 , G06F9/30076 , G06F9/30127 , G06F9/30145
摘要： Techniques are disclosed relating to a processor including instruction support for performing a Montgomery multiplication. The processor may issue, for execution, programmer-selectable instruction from a defined instruction set architecture (ISA). The processor may include an instruction execution unit configured to receive instructions including a first instance of a Montgomery-multiply instruction defined within the ISA. The Montgomery-multiply instruction is executable by the processor to operate on at least operands A, B, and N residing in respective portions of a general-purpose register file of the processor, where at least one of operands A, B, N spans at least two registers of general-purpose register file. The instruction execution unit is configured to calculate P mod N in response to receiving the first instance of the Montgomery-multiply instruction, where P is the product of at least operand A, operand B, and R^−1.
摘要翻译：公开了涉及包括用于执行蒙哥马利乘法的指令支持的处理器的技术。处理器可以从定义的指令集架构（ISA）发出执行编程器可选择的指令。处理器可以包括指令执行单元，其被配置为接收包括在ISA内定义的蒙哥马利乘法指令的第一实例的指令。蒙哥马利乘法指令可由处理器执行，以至少驻留在处理器的通用寄存器文件的相应部分中的操作数A，B和N操作，其中操作数A，B，N中的至少一个跨越最少两个通用寄存器寄存器。指令执行单元被配置为响应于接收到蒙哥马利乘法指令的第一实例来计算P mod N，其中P是至少操作数A，操作数B和R ^ -1的乘积。

10. 发明授权

US08213606B2 Method and apparatus for implementing processor instructions for accelerating public-key cryptography 有权
标题翻译：用于实现用于加速公钥密码术的处理器指令的方法和装置
公开(公告)号：US08213606B2
公开(公告)日：2012-07-03
申请号：US10789311
申请日：2004-02-27
申请人： Sheueling Chang Shantz , Leonard Rarick , Lawrence Spracklen , Hans Eberle , Nils Gura
发明人： Sheueling Chang Shantz , Leonard Rarick , Lawrence Spracklen , Hans Eberle , Nils Gura
IPC分类号： G06F21/00
CPC分类号： G06F7/5324 , G06F7/5318 , G06F7/5443 , G06F9/3001 , G06F9/30094 , G06F9/30101 , G06F9/3851
摘要： In response to executing an arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is fed back from a first carry save adder structure generating high order bits of the current arithmetic instruction to a second carry save adder tree structure being utilized to generate low order bits of the current arithmetic instruction to generate a result that represents the first number multiplied by the second number summed with the high order bits from the previously executed arithmetic instruction. Execution of the arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number, the third number being fed to the carry save adder tree structure.
摘要翻译：响应于执行算术指令，将第一数乘以第二数，并且从先前执行的单个算术指令的部分结果从当前算术指令的高阶位产生的第一进位保存加法器结构反馈给第二进位保存加法器树结构用于生成当前算术指令的低位比特，以生成表示与先前执行的算术指令相加的与高位相加的第二数的第一数字的结果。可以执行算术指令可以产生表示第一数乘以与部分结果相加的第二数的结果，并且还与第三数相加，第三数被馈送到进位保存加法器树结构。

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