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1. 发明申请

US20160093344A1 METHOD, APPARATUS AND SYSTEM TO MANAGE IMPLICIT PRE-CHARGE COMMAND SIGNALING 有权
标题翻译：方法，装置和系统来管理隐式预充电指令信号
公开(公告)号：US20160093344A1
公开(公告)日：2016-03-31
申请号：US14498509
申请日：2014-09-26
申请人： John B. Halbert , Bruce A. Christenson , Kuljit S. Bains
发明人： John B. Halbert , Bruce A. Christenson , Kuljit S. Bains
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , G06F13/1668 , G06F13/1689 , G06F21/79 , G11C7/1045 , G11C7/1048 , G11C7/1063 , G11C7/109 , G11C11/4076 , G11C11/4093 , G11C11/4094 , Y02D10/14
摘要： Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.
摘要翻译：用于在存储器控制器和存储器件之间交换信息的技术和机制。在一个实施例中，存储器控制器接收指示存储器设备访问该存储器设备的临时统一激活命令的阈值数量的信息。由信息指示的阈值数小于待处理的合并激活命令的理论最大数量，基于存储器件的定时参数定义的理论最大数量。在另一个实施例中，存储器控制器基于指示阈值数量的信息来限制合并的激活命令到存储器设备的通信。

2. 发明授权

US07694060B2 Systems with variable link widths based on estimated activity levels 失效
标题翻译：基于估计活动水平的具有可变链路宽度的系统
公开(公告)号：US07694060B2
公开(公告)日：2010-04-06
申请号：US11155857
申请日：2005-06-17
申请人： James A. McCall , Bruce A. Christenson
发明人： James A. McCall , Bruce A. Christenson
IPC分类号： G06F1/00
CPC分类号： G06F13/4068 , Y02D10/14 , Y02D10/151
摘要： In some embodiments, a chip includes transmitters and receivers, and control circuitry. The control circuitry to cause some of the transmitters and receivers to be inoperative in response to an estimated activity level being in a first range, while others of the transmitters and receivers remain operative. Other embodiments are described and/or claimed.
摘要翻译：在一些实施例中，芯片包括发射机和接收机以及控制电路。所述控制电路使得一些发射器和接收器响应于估计的活动电平处于第一范围而不起作用，而发射器和接收器中的另一个保持有效。描述和/或要求保护其他实施例。

3. 发明申请

US20090327596A1 MEMORY CONTROLLER USING TIME-STAGGERED LOCKSTEP SUB-CHANNELS WITH BUFFERED MEMORY 有权
标题翻译：使用具有缓冲存储器的时间延迟锁定子通道的存储器控制器
公开(公告)号：US20090327596A1
公开(公告)日：2009-12-31
申请号：US12163672
申请日：2008-06-27
申请人： Bruce A. Christenson , Rajat Agarwal
发明人： Bruce A. Christenson , Rajat Agarwal
IPC分类号： G06F12/00 , G06F9/46
CPC分类号： G06F13/1684
摘要： Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two double-data-rate (DDR) DRAM sub-channels behind a memory buffer (e.g., FB-DIMM or buffer-on-board). The two commands are in time-staggered lockstep. The time-stagger allows data coming back from the two back-side DDR sub-channels to flow naturally on the host channel without conflict. Multiple DIMMs can be used to obtain chip-fail ECC capabilities and to reclaim at least some of the lost performance imposed by the burst-length of 4 s typically associated with dual channel lockstep memory controllers. The techniques can be implemented, for instance, with a buffered memory solution such as fully buffered DIMM (FB-DIMM) or buffer-on-board configurations.
摘要翻译：公开了用于双通道锁步配置的存储器控制技术。根据一个示例实施例，存储器控制器向存储器缓冲器（例如，FB-DIMM或板上缓冲器）后面的两个双数据速率（DDR）DRAM子通道发出两个突发长度的4个DRAM命令。这两个命令处于时间交错的锁定状态。时间错误允许从两个背面的DDR子通道返回的数据在主机通道上自然流动而没有冲突。可以使用多个DIMM来获得芯片故障ECC功能，并回收通常与双通道锁步存储器控制器相关联的4秒的突发长度所施加的至少一些丢失的性能。这些技术可以实现，例如使用缓冲存储器解决方案，例如完全缓冲的DIMM（FB-DIMM）或板载缓冲器配置。

4. 发明申请

US20080320249A1 FULLY BUFFERED DIMM READ DATA SUBSTITUTION FOR WRITE ACKNOWLEDGEMENT 有权
标题翻译：完全缓冲的DIMM读取写入确认的数据替代
公开(公告)号：US20080320249A1
公开(公告)日：2008-12-25
申请号：US12202088
申请日：2008-08-29
申请人： James W. Alexander , Rajat Agarwal , Bruce A. Christenson , Kai Cheng
发明人： James W. Alexander , Rajat Agarwal , Bruce A. Christenson , Kai Cheng
IPC分类号： G06F12/16 , G06F12/00
CPC分类号： G06F13/4234 , G06F13/1673
摘要： A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.
摘要翻译：内存控制器使用一种方案来从重放队列中退出两个条目，这是由于单个无错误的响应。有利地，重放队列中的条目可以比常规系统更早地退出，从而最小化重播队列的大小。

5. 发明授权

US07093059B2 Read-write switching method for a memory controller 有权
标题翻译：用于存储器控制器的读写切换方法
公开(公告)号：US07093059B2
公开(公告)日：2006-08-15
申请号：US10335485
申请日：2002-12-31
申请人： Bruce A. Christenson
发明人： Bruce A. Christenson
IPC分类号： G06F12/02 , G11C8/12
CPC分类号： G06F13/1647 , G06F13/161
摘要： A system includes a memory device. The memory device has a first bank and a second bank. A memory controller has a write request queue to store write requests. When a read bank conflict exists between a first read request to the first bank and a second read request to the first bank, a first write request is executed to the second bank during a delay. The delay takes place after the first read request is executed and before the second read request is executed.
摘要翻译：系统包括存储器件。存储器件具有第一存储体和第二存储体。存储器控制器具有用于存储写请求的写请求队列。当在第一存储体的第一读取请求与第一存储体的第二读取请求之间存在读取存储体冲突时，在延迟期间向第二存储体执行第一写入请求。延迟发生在执行第一个读取请求之后并且在执行第二个读取请求之前。

6. 发明授权

US08060692B2 Memory controller using time-staggered lockstep sub-channels with buffered memory 有权
标题翻译：内存控制器使用带有缓冲内存的时间交错锁步子通道
公开(公告)号：US08060692B2
公开(公告)日：2011-11-15
申请号：US12163672
申请日：2008-06-27
申请人： Bruce A. Christenson , Rajat Agarwal
发明人： Bruce A. Christenson , Rajat Agarwal
IPC分类号： G06F12/00
CPC分类号： G06F13/1684
摘要： Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two double-data-rate (DDR) DRAM sub-channels behind a memory buffer (e.g., FB-DIMM or buffer-on-board). The two commands are in time-staggered lockstep. The time-stagger allows data coming back from the two back-side DDR sub-channels to flow naturally on the host channel without conflict. Multiple DIMMs can be used to obtain chip-fail ECC capabilities and to reclaim at least some of the lost performance imposed by the burst-length of 4 s typically associated with dual channel lockstep memory controllers. The techniques can be implemented, for instance, with a buffered memory solution such as fully buffered DIMM (FB-DIMM) or buffer-on-board configurations.
摘要翻译：公开了用于双通道锁步配置的存储器控制技术。根据一个示例实施例，存储器控制器向存储器缓冲器（例如，FB-DIMM或板上缓冲器）后面的两个双数据速率（DDR）DRAM子通道发出两个突发长度的4个DRAM命令。这两个命令处于时间交错的锁定状态。时间错误允许从两个背面的DDR子通道返回的数据在主机通道上自然流动而没有冲突。可以使用多个DIMM来获得芯片故障ECC功能，并回收通常与双通道锁步存储器控制器相关联的4秒的突发长度所施加的至少一些丢失的性能。这些技术可以实现，例如使用缓冲存储器解决方案，例如完全缓冲的DIMM（FB-DIMM）或板载缓冲器配置。

7. 发明授权

US07444479B2 Fully buffered DIMM read data substitution for write acknowledgement 失效
标题翻译：全缓冲DIMM读取数据替代写入确认
公开(公告)号：US07444479B2
公开(公告)日：2008-10-28
申请号：US11321322
申请日：2005-12-28
申请人： James W. Alexander , Rajat Agarwal , Bruce A. Christenson , Kai Cheng
发明人： James W. Alexander , Rajat Agarwal , Bruce A. Christenson , Kai Cheng
IPC分类号： G06F12/16
CPC分类号： G06F13/4234 , G06F13/1673
摘要： A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.
摘要翻译：内存控制器使用一种方案来从重放队列中退出两个条目，这是由于单个无错误的响应。有利地，重放队列中的条目可以比常规系统更早地退出，从而最小化重播队列的大小。

8. 发明授权

US09530468B2 Method, apparatus and system to manage implicit pre-charge command signaling 有权
标题翻译：用于管理隐式预充电命令信令的方法，装置和系统
公开(公告)号：US09530468B2
公开(公告)日：2016-12-27
申请号：US14498509
申请日：2014-09-26
申请人： John B. Halbert , Bruce A. Christenson , Kuljit S. Bains
发明人： John B. Halbert , Bruce A. Christenson , Kuljit S. Bains
IPC分类号： G06F12/00 , G11C7/10 , G11C11/4076 , G11C11/4093 , G11C11/4094 , G06F13/16 , G06F21/79
CPC分类号： G11C7/1072 , G06F13/1668 , G06F13/1689 , G06F21/79 , G11C7/1045 , G11C7/1048 , G11C7/1063 , G11C7/109 , G11C11/4076 , G11C11/4093 , G11C11/4094 , Y02D10/14
摘要： Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.
摘要翻译：用于在存储器控制器和存储器件之间交换信息的技术和机制。在一个实施例中，存储器控制器接收指示存储器设备访问该存储器设备的临时统一激活命令的阈值数量的信息。由信息指示的阈值数小于待处理的合并激活命令的理论最大数量，基于存储器件的定时参数定义的理论最大数量。在另一个实施例中，存储器控制器基于指示阈值数量的信息来限制合并的激活命令到存储器设备的通信。

9. 发明授权

US07941618B2 Fully buffered DIMM read data substitution for write acknowledgement 有权
标题翻译：全缓冲DIMM读取数据替代写入确认
公开(公告)号：US07941618B2
公开(公告)日：2011-05-10
申请号：US12202088
申请日：2008-08-29
申请人： James W. Alexander , Rajat Agarwal , Bruce A. Christenson , Kai Cheng
发明人： James W. Alexander , Rajat Agarwal , Bruce A. Christenson , Kai Cheng
IPC分类号： G06F12/16
CPC分类号： G06F13/4234 , G06F13/1673
摘要： A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.
摘要翻译：内存控制器使用一种方案来从重放队列中退出两个条目，这是由于单个无错误的响应。有利地，重放队列中的条目可以比常规系统更早地退出，从而最小化重播队列的大小。

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