专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07876618B2 Non-volatile memory with reduced leakage current for unselected blocks and method for operating same 有权
标题翻译：用于未选择块的漏电流减少的非易失性存储器及其操作方法
公开(公告)号：US07876618B2
公开(公告)日：2011-01-25
申请号：US12409020
申请日：2009-03-23
申请人： Sanghyun Lee , Masaaki Higashitani , Shinji Sato , Chih-Ming Wang
发明人： Sanghyun Lee , Masaaki Higashitani , Shinji Sato , Chih-Ming Wang
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08
摘要： A memory device with reduced leakage current during programming and sense operations, and a method for operating such a memory device. In a non-volatile memory device, current leakage at the drain select gates of NAND strings can occur in unselected blocks when a selected block undergoes a program or read operation, and the bit lines are shared by the blocks. In one approach, in which a common transfer gate driver is provided for both blocks, the drain select gates are pre-charged at an optimum level, which minimizes leakage, and subsequently floated while a program or read voltage is applied to a selected word line in the selected block. In another approach, a separate transfer gate driver is provided for the unselected block so that the optimal select gate voltage can be driven in the unselected block, even while the program or read voltage is applied in the selected block.
摘要翻译：在编程和感测操作期间具有减小的漏电流的存储器件，以及用于操作这种存储器件的方法。在非易失性存储器件中，当所选择的块经历程序或读取操作，并且位线由块共享时，在NAND串的漏极选择栅极处的电流泄漏可能发生在未选择的块中。在其中为两个块提供公共传输栅极驱动器的一种方法中，漏极选择栅极以最佳电平进行预充电，这使泄漏最小化，随后浮动，同时将程序或读取电压施加到所选择的字线在所选的块中。在另一种方法中，为未选择的块提供单独的传输栅极驱动器，使得即使在所选择的块中施加编程或读取电压，也可以在未选择的块中驱动最佳选择栅极电压。

2. 发明申请

US20100238729A1 NON-VOLATILE MEMORY WITH REDUCED LEAKAGE CURRENT FOR UNSELECTED BLOCKS AND METHOD FOR OPERATING SAME 有权
标题翻译：具有减少漏电流的非易失性存储器用于未经选择的块及其操作方法
公开(公告)号：US20100238729A1
公开(公告)日：2010-09-23
申请号：US12409020
申请日：2009-03-23
申请人： Sanghyun Lee , Masaaki Higashitani , Shinji Sato , Chih-Ming Wang
发明人： Sanghyun Lee , Masaaki Higashitani , Shinji Sato , Chih-Ming Wang
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08
摘要： A memory device with reduced leakage current during programming and sense operations, and a method for operating such a memory device. In a non-volatile memory device, current leakage at the drain select gates of NAND strings can occur in unselected blocks when a selected block undergoes a program or read operation, and the bit lines are shared by the blocks. In one approach, in which a common transfer gate driver is provided for both blocks, the drain select gates are pre-charged at an optimum level, which minimizes leakage, and subsequently floated while a program or read voltage is applied to a selected word line in the selected block. In another approach, a separate transfer gate driver is provided for the unselected block so that the optimal select gate voltage can be driven in the unselected block, even while the program or read voltage is applied in the selected block.
摘要翻译：在编程和感测操作期间具有减小的漏电流的存储器件，以及用于操作这种存储器件的方法。在非易失性存储器件中，当所选择的块经历程序或读取操作，并且位线由块共享时，在NAND串的漏极选择栅极处的电流泄漏可能发生在未选择的块中。在其中为两个块提供公共传输栅极驱动器的一种方法中，漏极选择栅极以最佳电平进行预充电，这使泄漏最小化，随后浮动，同时将程序或读取电压施加到所选择的字线在所选的块中。在另一种方法中，为未选择的块提供单独的传输栅极驱动器，使得即使在所选择的块中施加编程或读取电压，也可以在未选择的块中驱动最佳选择栅极电压。

3. 发明申请

US20120243337A1 P-/METAL FLOATING GATE NON-VOLATILE STORAGE ELEMENT 有权
标题翻译： P- /金属浮动门非易失存储元件
公开(公告)号：US20120243337A1
公开(公告)日：2012-09-27
申请号：US13153964
申请日：2011-06-06
申请人： Sanghyun Lee , Mohan Dunga , Masaaki Higashitani , Tuan Pham , Franz Kreupl
发明人： Sanghyun Lee , Mohan Dunga , Masaaki Higashitani , Tuan Pham , Franz Kreupl
IPC分类号： G11C16/10 , G11C16/04 , H01L21/336 , H01L29/788
CPC分类号： H01L21/28273 , H01L27/11524 , H01L27/11529 , H01L29/42324
摘要： Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.
摘要翻译：本文公开了具有P- /金属浮动栅极的非易失性存储元件。浮栅可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有金属区域。隧道氧化物附近的P-区域有助于提供良好的数据保留。控制栅极附近的金属区域有助于实现控制栅极和浮动栅极之间良好的耦合比。因此，非易失性存储元件的编程是有效的。此外，擦除非易失性存储元件可能是有效的。在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

4. 发明授权

US08853763B2 Integrated circuits with sidewall nitridation 有权
标题翻译：具有侧壁氮化的集成电路
公开(公告)号：US08853763B2
公开(公告)日：2014-10-07
申请号：US13607375
申请日：2012-09-07
申请人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
发明人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
IPC分类号： H01L29/76 , H01L27/115 , H01L29/66 , H01L21/28
CPC分类号： H01L27/11548 , H01L21/2815 , H01L27/11529 , H01L29/66825
摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.
摘要翻译：半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

5. 发明申请

US20120326220A1 Integrated Circuits With Sidewall Nitridation 有权
标题翻译：集成电路与侧壁氮化
公开(公告)号：US20120326220A1
公开(公告)日：2012-12-27
申请号：US13607375
申请日：2012-09-07
申请人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
发明人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
IPC分类号： H01L29/78
CPC分类号： H01L27/11548 , H01L21/2815 , H01L27/11529 , H01L29/66825
摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.
摘要翻译：半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

6. 发明授权

US08503229B2 P-/Metal floating gate non-volatile storage element 有权
标题翻译： P- /金属浮动门非易失性存储元件
公开(公告)号：US08503229B2
公开(公告)日：2013-08-06
申请号：US13153964
申请日：2011-06-06
申请人： Sanghyun Lee , Mohan Dunga , Masaaki Higashitani , Tuan Pham , Franz Kreupl
发明人： Sanghyun Lee , Mohan Dunga , Masaaki Higashitani , Tuan Pham , Franz Kreupl
IPC分类号： G11C11/34 , G11C16/04 , H01L29/94 , H01L21/00 , H01L21/8238
CPC分类号： H01L21/28273 , H01L27/11524 , H01L27/11529 , H01L29/42324
摘要： Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.
摘要翻译：本文公开了具有P- /金属浮动栅极的非易失性存储元件。浮栅可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有金属区域。隧道氧化物附近的P-区域有助于提供良好的数据保留。控制栅极附近的金属区域有助于实现控制栅极和浮动栅极之间良好的耦合比。因此，非易失性存储元件的编程是有效的。此外，擦除非易失性存储元件可能是有效的。在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

7. 发明授权

US08288293B2 Integrated circuit fabrication using sidewall nitridation processes 有权
标题翻译：使用侧壁氮化工艺的集成电路制造
公开(公告)号：US08288293B2
公开(公告)日：2012-10-16
申请号：US12763963
申请日：2010-04-20
申请人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
发明人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
IPC分类号： H01L21/469
CPC分类号： H01L27/11548 , H01L21/2815 , H01L27/11529 , H01L29/66825
摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.
摘要翻译：半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

8. 发明申请

US20120228691A1 PN FLOATING GATE NON-VOLATILE STORAGE ELEMENT 审中-公开
标题翻译： PN浮动门非易失存储元件
公开(公告)号：US20120228691A1
公开(公告)日：2012-09-13
申请号：US13072130
申请日：2011-03-25
申请人： Mohan Dunga , Sanghyun Lee , Masaaki Higashitani , Tuan Pham
发明人： Mohan Dunga , Sanghyun Lee , Masaaki Higashitani , Tuan Pham
IPC分类号： H01L29/788 , H01L21/336 , H01L21/28
CPC分类号： H01L29/66825 , G11C11/5642 , G11C16/0408 , G11C16/3418 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/40114 , H01L29/7881
摘要： Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.
摘要翻译：本文公开了具有PN浮动栅极的非易失性存储元件。浮置栅极可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有N +区域。在一些实施例中，隧道氧化物附近的P-区域有助于提供良好的数据保留。在一些实施例中，控制栅极附近的N +区域有助于实现控制栅极和浮置栅极之间良好的耦合比。因此，非易失性存储元件的编程是有效的。也可以有效地擦除非易失性存储元件。在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

9. 发明申请

US20100270608A1 Integrated Circuits And Fabrication Using Sidewall Nitridation Processes 有权
标题翻译：集成电路和使用侧壁氮化工艺的制造
公开(公告)号：US20100270608A1
公开(公告)日：2010-10-28
申请号：US12763963
申请日：2010-04-20
申请人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
发明人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
IPC分类号： H01L29/792 , H01L21/28 , H01L21/76
CPC分类号： H01L27/11548 , H01L21/2815 , H01L27/11529 , H01L29/66825
摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.
摘要翻译：半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

10. 发明授权

US08951859B2 Method for fabricating passive devices for 3D non-volatile memory 有权
标题翻译：用于制造3D非易失性存储器的无源器件的方法
公开(公告)号：US08951859B2
公开(公告)日：2015-02-10
申请号：US13301560
申请日：2011-11-21
申请人： Masaaki Higashitani , Peter Rabkin
发明人： Masaaki Higashitani , Peter Rabkin
IPC分类号： H01L21/8239 , H01L29/792 , H01L49/02 , H01L27/115
CPC分类号： H01L29/7926 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L28/20 , H01L28/87 , H01L28/88
摘要： A method for fabricating passive devices such as resistors and capacitors for a 3D non-volatile memory device. In a peripheral area of a substrate, alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide are provided in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are formed above the stack. Contact structures are formed which extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel or serially by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers. The passive device can be fabricated concurrently with a 3D memory array using common processing steps.
摘要翻译：一种用于制造用于3D非易失性存储器件的诸如电阻器和电容器的无源器件的方法。在衬底的外围区域中，叠层中提供诸如氧化物和诸如重掺杂多晶硅或金属硅化物的导电材料的电介质的交替层。衬底包括连接到电路的一个或多个下部金属层。在堆叠上方形成一个或多个上金属层。形成了从导电材料层延伸到一个或多个上金属层的部分的接触结构，使得导电材料层彼此平行或连续地由接触结构和至少一个上金属层。附加接触结构可以将电路连接到一个或多个上金属层。可以使用常规的处理步骤与3D存储器阵列同时地制造无源器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式