专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07515459B2 Method of programming a memory cell array using successive pulses of increased duration 有权
标题翻译：使用增加的持续时间的连续脉冲对存储器单元阵列进行编程的方法
公开(公告)号：US07515459B2
公开(公告)日：2009-04-07
申请号：US11315129
申请日：2005-12-23
申请人： Sang-beom Kang , Du-eung Kim , Beak-hyung Cho , Hye-jin Kim
发明人： Sang-beom Kang , Du-eung Kim , Beak-hyung Cho , Hye-jin Kim
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A method of programming a memory array including a plurality of memory cells is provided. The memory cells may include phase-change memory elements. In one aspect, the method includes applying in succession first through nth current pulses to each of the memory cells to be programmed to a first state (e.g., a crystalline state), where a current amplitude of the first through nth current pulses decreases with each successive pulse, and where a pulse duration of the first through nth current pulses increases with each successive pulse.
摘要翻译：提供了一种编程包括多个存储单元的存储器阵列的方法。存储器单元可以包括相变存储元件。在一个方面，该方法包括将第一至第n电流脉冲连续地应用于要被编程到第一状态（例如，结晶状态）的每个存储器单元，其中第一至第n电流脉冲的电流幅度随着每个连续脉冲，并且其中第一至第n电流脉冲的脉冲持续时间随着每个连续脉冲而增加。

2. 发明申请

US20060209616A1 Phase change memory device and associated wordline driving circuit 失效
公开(公告)号：US20060209616A1
公开(公告)日：2006-09-21
申请号：US11319604
申请日：2005-12-29
申请人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
发明人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
IPC分类号： G11C8/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0028
摘要： A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a first voltage level when the global wordline and the address signal have a first logic state and at a second voltage level when the global wordline or the address signal have a second logic state.

3. 发明授权

US07548446B2 Phase change memory device and associated wordline driving circuit 失效
标题翻译：相变存储器件和相关的字线驱动电路
公开(公告)号：US07548446B2
公开(公告)日：2009-06-16
申请号：US11319604
申请日：2005-12-29
申请人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
发明人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0028
摘要： A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a first voltage level when the global wordline and the address signal have a first logic state and at a second voltage level when the global wordline or the address signal have a second logic state.
摘要翻译：半导体存储器件包括多个字线驱动电路，其适于响应于全局字线和地址信号的逻辑状态来控制子字线的电压电平。字线驱动电路包括第一和第二晶体管，其被配置为当全局字线和地址信号具有第一逻辑状态并且当全局字线或地址信号具有第一电压电平时，将子字线保持在第一电压电平第二逻辑状态。

4. 发明申请

US20060221679A1 Method of programming memory cell array 有权
标题翻译：编程存储单元阵列的方法
公开(公告)号：US20060221679A1
公开(公告)日：2006-10-05
申请号：US11315129
申请日：2005-12-23
申请人： Sang-beom Kang , Du-eung Kim , Baek-hyung Cho , Hye-jin Kim
发明人： Sang-beom Kang , Du-eung Kim , Baek-hyung Cho , Hye-jin Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A method of programming a memory array including a plurality of memory cells is provided. The memory cells may include phase-change memory elements. In one aspect, the method includes applying in succession first through nth current pulses to each of the memory cells to be programmed to a first state (e.g., a crystalline state), where a current amplitude of the first through nth current pulses decreases with each successive pulse, and where a pulse duration of the first through nth current pulses increases with each successive pulse.
摘要翻译：提供了一种编程包括多个存储单元的存储器阵列的方法。存储器单元可以包括相变存储元件。在一个方面，所述方法包括首先连续地将每个存储单元连续施加到要编程到第一状态（例如，结晶状态）的第n个/ 第一至第n个电流脉冲随着每个连续脉冲而减小，并且其中第一至第n个电流脉冲的脉冲持续时间随每个连续脉冲而增加。

5. 发明授权

US08179711B2 Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell 有权
标题翻译：具有堆叠存储单元的半导体存储器件和制造堆叠存储单元的方法
公开(公告)号：US08179711B2
公开(公告)日：2012-05-15
申请号：US12273225
申请日：2008-11-18
申请人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
发明人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C5/02 , G11C7/18 , G11C11/15 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/71 , G11C2213/74 , G11C2213/79 , H01L27/24
摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.
摘要翻译：在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。在一个示例中，控制晶体管的数量是两个。半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

6. 发明授权

US07573766B2 Phase change random access memory and method of testing the same 有权
标题翻译：相变随机存取存储器和测试方法相同
公开(公告)号：US07573766B2
公开(公告)日：2009-08-11
申请号：US11898125
申请日：2007-09-10
申请人： Byung-gil Choi , Beak-hyung Cho , Du-eung Kim , Chang-han Choi , Yu-hwan Ro
发明人： Byung-gil Choi , Beak-hyung Cho , Du-eung Kim , Chang-han Choi , Yu-hwan Ro
IPC分类号： G11C29/00
CPC分类号： G11C13/0004 , G11C29/50 , G11C2029/1204 , G11C2029/5006
摘要： Provided is a method of testing a phase change random access memory (PRAM). The method may include providing a plurality of PRAM cells each coupled between each of a plurality of first lines and each of a plurality of second lines intersecting the first lines, selecting at least one of the plurality of first lines while deselecting the remaining first lines and the plurality of second lines, pre-charging the selected at least one of the plurality of first lines to a predetermined or given voltage level, and sensing a change in the voltage level of the selected first line while supplying a monitoring voltage to the selected first line.
摘要翻译：提供了一种测试相变随机存取存储器（PRAM）的方法。该方法可以包括提供多个PRAM单元，每个PRAM单元分别耦合在多个第一线中的每一条与多条第一线相交的多条第二线中的每条之间，同时选择多条第一条线中的至少一条，同时取消选择其余的第一条线，所述多个第二线路将所选择的所述多个第一线路中的至少一个预充电到预定或给定的电压电平，并且感测所选择的第一线路的电压电平的变化，同时向所选择的第一线路提供监视电压线。

7. 发明申请

US20070195591A1 Layout method of a semiconductor memory device 有权
标题翻译：半导体存储器件的布局方法
公开(公告)号：US20070195591A1
公开(公告)日：2007-08-23
申请号：US11790444
申请日：2007-04-25
申请人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
发明人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
IPC分类号： G11C5/06 , G11C5/02 , G11C11/00
CPC分类号： G11C7/18 , G11C5/025 , G11C13/0004
摘要： The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite the first side. The method further includes connecting the first bit line selection circuits with respective odd-numbered local bit lines of the variable resistive memory cell block, and connecting the second bit line selection circuits with respective even-numbered local bit lines of the variable resistive memory cell block. The method still further includes selectively connecting respective odd-numbered local bit lines to a global bit line using the first bit line selection circuits, and selectively connecting respective even-numbered local bit lines to the global bit line using the second bit line selection circuits.
摘要翻译：半导体器件的布局方法包括在可变电阻存储器单元块的第一侧定位多个第一位线选择电路，并且将多个第二位线选择电路定位在可变电阻存储器单元块的第二侧第一面相反该方法还包括将第一位线选择电路与可变电阻存储单元块的相应奇数本地位线连接，并将第二位线选择电路与可变电阻存储单元块的各个偶数本地位线连接。该方法还包括使用第一位线选择电路选择性地将相应的奇数本地位线连接到全局位线，并且使用第二位线选择电路选择性地将各偶数本地位线连接到全局位线。

8. 发明申请

US20060285380A1 Phase change random access memory (PRAM) device 失效
标题翻译：相变随机存取存储器（PRAM）设备
公开(公告)号：US20060285380A1
公开(公告)日：2006-12-21
申请号：US11315130
申请日：2005-12-23
申请人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
发明人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
IPC分类号： G11C11/00
CPC分类号： G11C7/18 , G11C5/025 , G11C13/0004
摘要： A phase change memory device includes a phase change memory cell block having alternating odd-numbered and even-numbered local bit lines, a global bit line, a plurality of first bit line selection circuits, and a plurality of second bit line selection circuits. The plurality of first bit line selection circuits are located at a first side of the phase change memory cell block and selectively connect respective odd-numbered local bit lines to the global bit line. The plurality of second bit line selection circuits are located at second side of the phase change memory cell block (opposite the first side) and selectively connect respective even-numbered local bit lines to the global bit line.
摘要翻译：相变存储器件包括具有交替的奇数和偶数编号的局部位线，全局位线，多个第一位线选择电路和多个第二位线选择电路的相变存储器单元块。多个第一位线选择电路位于相变存储单元块的第一侧，并且选择性地将各自的奇数本地位线连接到全局位线。多个第二位线选择电路位于相变存储单元块的第二侧（与第一侧相反），并且选择性地将各偶数的局部位线连接到全局位线。

9. 发明申请

US20050052904A1 Initial firing method and phase change memory device for performing firing effectively 有权
标题翻译：初始烧制方法和相变存储装置，用于有效地进行烧制
公开(公告)号：US20050052904A1
公开(公告)日：2005-03-10
申请号：US10929511
申请日：2004-08-30
申请人： Beak-hyung Cho , Du-eung Kim , Choong-keun Kwak
发明人： Beak-hyung Cho , Du-eung Kim , Choong-keun Kwak
IPC分类号： G11C13/02 , G11C11/00 , G11C16/20
CPC分类号： G11C13/0004 , G11C2013/0083 , Y10S977/754
摘要： A firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation are described. The phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and a driving unit. Each memory cell array block has phase change memory cells. The counter clock generation unit outputs first through third counter clock signals in response to an external clock signal and a firing mode signal, wherein the first through third counter clock signals have different cycles. The decoding unit, in response to the first through third counter clock signals, outputs a block address which selects one of the plurality of memory cell array blocks, word line addresses which enable word lines of the selected memory cell array block, and a redundant word line address which enables a redundant word line of the selected memory cell array block. The driving unit applies a firing current to the memory cell array blocks in response to the firing mode signal. According to the phase change memory device and the initial firing method, the time taken to perform the initial firing operation can be reduced. In addition, since the numbers of the needed signals are minimized, a large number of chips on a single wafer can be simultaneously tested.
摘要翻译：描述能够有效地执行点火操作的相变存储器件和相变存储器的点火方法。相变存储器件包括多个存储单元阵列块，计数器时钟生成单元，解码单元和驱动单元。每个存储单元阵列块具有相变存储单元。计数器时钟产生单元响应于外部时钟信号和触发模式信号输出第一至第三计数器时钟信号，其中第一至第三计数器时钟信号具有不同的周期。解码单元响应于第一至第三计数器时钟信号输出选择多个存储单元阵列块中的一个的块地址，使得能够选择的存储单元阵列块的字线的字线地址和冗余字行地址，其使能所选存储单元阵列块的冗余字线。驱动单元响应于点火模式信号向存储单元阵列块施加点火电流。根据相变存储器件和初始烧制方法，可以减少执行初始点火操作所花费的时间。此外，由于所需信号的数量最小化，可以同时测试单个晶片上的大量芯片。

10. 发明授权

US07460386B2 Layout method of a semiconductor memory device 有权
标题翻译：半导体存储器件的布局方法
公开(公告)号：US07460386B2
公开(公告)日：2008-12-02
申请号：US11790444
申请日：2007-04-25
申请人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
发明人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
IPC分类号： G11C5/02 , G11C5/06 , G11C11/00
CPC分类号： G11C7/18 , G11C5/025 , G11C13/0004
摘要： The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite the first side. The method further includes connecting the first bit line selection circuits with respective odd-numbered local bit lines of the variable resistive memory cell block, and connecting the second bit line selection circuits with respective even-numbered local bit lines of the variable resistive memory cell block. The method still further includes selectively connecting respective odd-numbered local bit lines to a global bit line using the first bit line selection circuits, and selectively connecting respective even-numbered local bit lines to the global bit line using the second bit line selection circuits.
摘要翻译：半导体器件的布局方法包括在可变电阻存储器单元块的第一侧定位多个第一位线选择电路，并且将多个第二位线选择电路定位在可变电阻存储器单元块的第二侧第一面相反该方法还包括将第一位线选择电路与可变电阻存储单元块的相应奇数本地位线连接，并将第二位线选择电路与可变电阻存储单元块的各个偶数本地位线连接。该方法还包括使用第一位线选择电路选择性地将相应的奇数本地位线连接到全局位线，并且使用第二位线选择电路选择性地将各偶数本地位线连接到全局位线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式