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1. 发明授权

US08415227B2 High performance dielectric stack for DRAM capacitor 有权
公开(公告)号：US08415227B2
公开(公告)日：2013-04-09
申请号：US13220460
申请日：2011-08-29
申请人： Sandra Malhotra , Wim Deweerd , Hanhong Chen , Xiangxin Rui , Hiroyuki Ode , Mitsuhiro Horikawa , Kenichi Koyanagi
发明人： Sandra Malhotra , Wim Deweerd , Hanhong Chen , Xiangxin Rui , Hiroyuki Ode , Mitsuhiro Horikawa , Kenichi Koyanagi
IPC分类号： H01L21/20 , H01L21/31
CPC分类号： H01L28/60 , H01L28/40 , H01L28/75
摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

2. 发明申请

US20130052792A1 HIGH PERFORMANCE DIELECTRIC STACK FOR DRAM CAPACITOR 有权
标题翻译：用于DRAM电容器的高性能电介质堆叠
公开(公告)号：US20130052792A1
公开(公告)日：2013-02-28
申请号：US13220460
申请日：2011-08-29
申请人： Sandra Malhotra , Wim Deweerd , Hanhong Chen , Xiangxin Rui , Hiroyuki Ode , Mitsuhiro Horikawa , Kenichi Koyanagi
发明人： Sandra Malhotra , Wim Deweerd , Hanhong Chen , Xiangxin Rui , Hiroyuki Ode , Mitsuhiro Horikawa , Kenichi Koyanagi
IPC分类号： H01L21/02
CPC分类号： H01L28/60 , H01L28/40 , H01L28/75
摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
摘要翻译：描述了制造DRAM电容器堆叠的方法，其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。在退火步骤之后，高掺杂材料保持无定形，结晶含量小于30％。在退火步骤之后，轻掺杂或非掺杂材料变成结晶含量等于或大于30％的晶体。电介质多层堆叠保持高的k值，同时使漏电流和EOT值最小化。

3. 发明授权

US08574998B2 Leakage reduction in DRAM MIM capacitors 有权
标题翻译： DRAM MIM电容器的漏电减少
公开(公告)号：US08574998B2
公开(公告)日：2013-11-05
申请号：US13311368
申请日：2011-12-05
申请人： Sandra Malhotra , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui , Takashi Arao , Naonori Fujiwara
发明人： Sandra Malhotra , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui , Takashi Arao , Naonori Fujiwara
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01G4/1272 , H01G4/306 , H01G4/33 , H01L21/02175 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/022 , H01L21/0228
摘要： A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (
摘要翻译：用于减少DRAM MIM电容器中的漏电流的方法包括从非晶高掺杂材料，非晶高带隙材料以及轻掺杂或非掺杂材料形成多层电介质叠层。退火步骤后，高掺杂材料将保持无定形（<30％结晶）。在退火步骤之后，高带隙材料将保持无定形（<30％结晶）。在退火步骤之后，轻掺杂或非掺杂材料将变成晶体（> = 30％结晶）。高带隙材料形成在无定形高掺杂材料和轻掺杂材料和非掺杂材料之间，并提供通过多层电介质叠层的导电的中间屏障。

4. 发明申请

US20120235276A1 ELECTRODE TREATMENTS FOR ENHANCED DRAM PERFORMANCE 审中-公开
标题翻译：用于增强DRAM性能的电极处理
公开(公告)号：US20120235276A1
公开(公告)日：2012-09-20
申请号：US13051531
申请日：2011-03-18
申请人： Xiangxin Rui , Hanhong Chen , Edward Haywood , Sandra Malhotra , Takashi Arao , Naonori Fujiwara , Toshiyuki Hirota , Takakazu Kiyomura , Kenichi Koyanagi
发明人： Xiangxin Rui , Hanhong Chen , Edward Haywood , Sandra Malhotra , Takashi Arao , Naonori Fujiwara , Toshiyuki Hirota , Takakazu Kiyomura , Kenichi Koyanagi
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L28/60 , H01L21/02 , H01L27/1085 , H01L28/40
摘要： A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO2) on the first TiN electrode; depositing a dielectric material on the first layer of titanium dioxide; and depositing a second TiN electrode on the dielectric material.
摘要翻译：公开了一种用于制造动态随机存取存储器电容器的方法。该方法可以包括沉积第一氮化钛（TiN）电极; 在第一TiN电极上形成第一层二氧化钛（TiO 2）; 在第一层二氧化钛上沉积电介质材料; 以及在所述电介质材料上沉积第二TiN电极。

5. 发明申请

US20130143379A1 LEAKAGE REDUCTION IN DRAM MIM CAPACITORS 有权
标题翻译： DRAM MIM电容器中的漏电减少
公开(公告)号：US20130143379A1
公开(公告)日：2013-06-06
申请号：US13311368
申请日：2011-12-05
申请人： Sandra Malholtra , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui , Takashi Arao , Naonori Fujiwara
发明人： Sandra Malholtra , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui , Takashi Arao , Naonori Fujiwara
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01G4/1272 , H01G4/306 , H01G4/33 , H01L21/02175 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/022 , H01L21/0228
摘要： A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (
摘要翻译：用于减少DRAM MIM电容器中的漏电流的方法包括从非晶高掺杂材料，非晶高带隙材料以及轻掺杂或非掺杂材料形成多层电介质叠层。退火步骤后，高掺杂材料将保持无定形（<30％结晶）。在退火步骤之后，高带隙材料将保持无定形（<30％结晶）。在退火步骤之后，轻掺杂或非掺杂材料将变成晶体（> = 30％结晶）。高带隙材料形成在无定形高掺杂材料和轻掺杂材料和非掺杂材料之间，并提供通过多层电介质叠层的导电的中间屏障。

6. 发明申请

US20070148896A1 MEMORY WITH MEMORY CELLS THAT INCLUDE A MIM TYPE CAPACITOR WITH A LOWER ELECTRODE MADE FOR REDUCED RESISTANCE AT AN INTERFACE WITH A METAL FILM 审中-公开
标题翻译：具有存储器电池的存储器，其包括具有用于在具有金属膜的接口下具有降低电阻的较低电极的MIM型电容器
公开(公告)号：US20070148896A1
公开(公告)日：2007-06-28
申请号：US11563442
申请日：2006-11-27
申请人： Yoshitaka Nakamura , Hidekazu Goto , Isamu Asano , Mitsuhiro Horikawa , Keiji Kuroki , Hiroshi Sakuma , Kenichi Koyanagi , Tsuyoshi Kawagoe
发明人： Yoshitaka Nakamura , Hidekazu Goto , Isamu Asano , Mitsuhiro Horikawa , Keiji Kuroki , Hiroshi Sakuma , Kenichi Koyanagi , Tsuyoshi Kawagoe
IPC分类号： H01L21/20
CPC分类号： H01L28/65 , H01L21/7687 , H01L27/10814 , H01L27/10852
摘要： A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.
摘要翻译：一种半导体器件包括各自具有形成在半导体衬底的一个主表面上的用于存储器选择的MISFET的存储单元，以及由用于存储器选择的MISFET的源极和漏极的底部电连接到下部电极的电容元件经由电容绝缘膜经由形成在下电极上的第一金属层和上电极。下部电极的底部的厚度为30nm以上。具有高电离比和高方向性的溅射（例如PCM）适于形成下电极，以使电容器的底部仅较厚。

7. 发明授权

US07224016B2 Memory with memory cells that include a MIM type capacitor with a lower electrode made for reduced resistance at an interface with a metal film 有权
标题翻译：具有存储单元的存储器，其包括具有用于在与金属膜的界面处降低的电阻的下电极的MIM型电容器
公开(公告)号：US07224016B2
公开(公告)日：2007-05-29
申请号：US10777704
申请日：2004-02-13
申请人： Yoshitaka Nakamura , Hidekazu Goto , Isamu Asano , Mitsuhiro Horikawa , Keiji Kuroki , Hiroshi Sakuma , Kenichi Koyanagi , Tsuyoshi Kawagoe
发明人： Yoshitaka Nakamura , Hidekazu Goto , Isamu Asano , Mitsuhiro Horikawa , Keiji Kuroki , Hiroshi Sakuma , Kenichi Koyanagi , Tsuyoshi Kawagoe
IPC分类号： H01L21/8242
CPC分类号： H01L28/65 , H01L21/7687 , H01L27/10814 , H01L27/10852
摘要： A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.
摘要翻译：一种半导体器件包括各自具有形成在半导体衬底的一个主表面上的用于存储器选择的MISFET的存储单元，以及由用于存储器选择的MISFET的源极和漏极的底部电连接到下部电极的电容元件经由电容绝缘膜经由形成在下电极上的第一金属层和上电极。下部电极的底部的厚度为30nm以上。具有高电离比和高方向性的溅射（例如PCM）适于形成下电极，以使电容器的底部仅较厚。

8. 发明授权

US08880217B2 Picking system 有权
标题翻译：采摘系统
公开(公告)号：US08880217B2
公开(公告)日：2014-11-04
申请号：US13337818
申请日：2011-12-27
申请人： Tetsuro Izumi , Kenichi Koyanagi , Kenji Matsukuma , Yukio Hashiguchi
发明人： Tetsuro Izumi , Kenichi Koyanagi , Kenji Matsukuma , Yukio Hashiguchi
IPC分类号： G06F7/00 , G06K9/34
CPC分类号： G06K9/34
摘要： A picking system includes a conveyer, a robot, a main camera, and a control device. The conveyer conveys workpieces. The robot performs a holding operation and a moving operation on the workpieces. The main camera captures the transport path of the conveyer. The control device detects the workpiece on the basis of the image captured by the main camera and instructs the robot to perform the holding operation on the detected workpiece. Moreover, the control device instructs the robot to perform the holding operation on the overlapped workpieces when the overlapping of the workpieces is detected.
摘要翻译：拾取系统包括输送机，机器人，主摄像机和控制装置。输送机输送工件。机器人对工件执行保持操作和移动操作。主相机捕获输送机的输送路径。控制装置基于由主摄像机拍摄的图像来检测工件，并指示机器人对检测到的工件执行保持操作。此外，当检测到工件的重叠时，控制装置指示机器人对重叠的工件执行保持操作。

9. 发明授权

US07303973B2 ALD process for capacitor dielectric 有权
标题翻译：电容电介质的ALD工艺
公开(公告)号：US07303973B2
公开(公告)日：2007-12-04
申请号：US10630444
申请日：2003-07-29
申请人： Kenichi Koyanagi , Hiroshi Sakuma
发明人： Kenichi Koyanagi , Hiroshi Sakuma
IPC分类号： H01L21/20
CPC分类号： H01L21/0228 , H01L21/02175 , H01L21/31604 , H01L21/31683 , H01L27/10808 , H01L27/10852 , H01L28/91
摘要： Provided is a method for manufacturing a semiconductor device, including a dual-stage deposition step including: a first stage for introducing tantalum penta-ethoxide containing tantalum as a material gas into a reaction chamber in which a semiconductor substrate on a surface of which a lower electrode is made of ruthenium is placed to thus form a tantalum oxide film by a vapor-phase growth method such as a chemical vapor deposition method and the following second stage for removing from the reaction chamber the material gas introduced into the reaction chamber at the first stage and a byproduct produced at the first stage by introducing a nitrogen gas, and wherein the tantalum oxide film is formed on the semiconductor substrate, by repeating the dual-stage deposition step two or more times.
摘要翻译：本发明提供一种半导体装置的制造方法，其特征在于，包括：第一阶段，将含有钽的钽五乙酸盐作为原料气体引入反应室，其中表面上的半导体衬底的下层电极由钌制成，由此通过气相生长法如化学气相沉积法形成氧化钽膜，以及随后的第二阶段，用于从反应室除去在第一个反应室中引入反应室的原料气体通过引入氮气在第一阶段产生副产物，并且其中通过重复两级沉积步骤两次或更多次在半导体衬底上形成氧化钽膜。

10. 发明申请

US20070051310A1 Semiconductor manufacturing apparatus 有权
标题翻译：半导体制造装置
公开(公告)号：US20070051310A1
公开(公告)日：2007-03-08
申请号：US11511507
申请日：2006-08-29
申请人： Kenichi Koyanagi
发明人： Kenichi Koyanagi
IPC分类号： C23C16/00
CPC分类号： C23C16/45546 , C23C16/4412 , C23C16/45527 , C23C16/45578
摘要： A semiconductor manufacturing apparatus has a nozzle with a plurality of tiny holes. The nozzle Is connected to a vacuum pump through a valve without closing its end so as to be evacuated and purged independently of the reaction chamber.
摘要翻译：半导体制造装置具有具有多个微小孔的喷嘴。喷嘴通过阀门连接到真空泵，而不关闭其端部，以便独立于反应室进行抽真空和净化。

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